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iverilog/tgt-fpga
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steve 5976e7078c Xilinx uses GROUND and VCC as pin names for the 
GND and VCC devices.

 Connect the top end of the EQ chain to the MUXCY
 instead of to the LUT. The MUXCY has the real output.
 		2001-09-12 04:35:25 +00:00
..
.cvsignore Add the fpga target. 2001-08-28 04:14:20 +00:00
Makefile.in Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00
configure.in Add the fpga target. 2001-08-28 04:14:20 +00:00
d-generic-edif.c Virtex support for mux devices and adders 2001-09-09 22:23:28 +00:00
d-generic.c Rearrange the XNF code generator to be generic-xnf 2001-09-02 21:33:07 +00:00
d-virtex.c Xilinx uses GROUND and VCC as pin names for the 2001-09-12 04:35:25 +00:00
device.h Rearrange the XNF code generator to be generic-xnf 2001-09-02 21:33:07 +00:00
fpga.c Rearrange the XNF code generator to be generic-xnf 2001-09-02 21:33:07 +00:00
fpga.txt Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00
fpga_priv.h Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00
gates.c Virtex support for mux devices and adders 2001-09-09 22:23:28 +00:00
mangle.c Rearrange the XNF code generator to be generic-xnf 2001-09-02 21:33:07 +00:00
tables.c Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00