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mirror of https://github.com/steveicarus/iverilog.git synced 2026-08-28 16:53:45 +02:00
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iverilog/tgt-fpga
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steve 36d36d99f3 Generate BUF devices for bufz logic.
2001-10-11 00:12:28 +00:00
..
.cvsignore
Add the fpga target.
2001-08-28 04:14:20 +00:00
configure.in
Fix some Cygwin DLL handling. (Venkat Iyer)
2001-09-30 16:45:10 +00:00
d-generic-edif.c
Suppor the PAD attribute on signals.
2001-09-16 01:48:16 +00:00
d-generic.c
Suppor the PAD attribute on signals.
2001-09-16 01:48:16 +00:00
d-virtex.c
Generate BUF devices for bufz logic.
2001-10-11 00:12:28 +00:00
device.h
Suppor the PAD attribute on signals.
2001-09-16 01:48:16 +00:00
fpga_priv.h
Separate the virtex and generic-edif code generators.
2001-09-06 04:28:39 +00:00
fpga.c
Suppor the PAD attribute on signals.
2001-09-16 01:48:16 +00:00
fpga.txt
Support the cellref attribute.
2001-09-16 22:26:47 +00:00
gates.c
Virtex support for mux devices and adders
2001-09-09 22:23:28 +00:00
Makefile.in
Separate the virtex and generic-edif code generators.
2001-09-06 04:28:39 +00:00
mangle.c
Make configure detect malloc.h
2001-09-15 18:27:04 +00:00
tables.c
Separate the virtex and generic-edif code generators.
2001-09-06 04:28:39 +00:00
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