iverilog/vhdlpp
Cary R 90cf0e5794 VHDL-10: fix a compile warning and add some missing newlines 2015-12-19 10:50:42 -08:00
..
Makefile.in vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
README.txt
architec.cc
architec.h
architec_debug.cc
architec_elaborate.cc vhdlpp: Removed conversion of '*_edge(sig)' to 'always begin..end @(*edge sig)'. 2015-06-24 23:53:33 +02:00
architec_emit.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
compiler.cc
compiler.h
debug.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
entity.cc
entity.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
entity_elaborate.cc
entity_emit.cc vhdlpp: generics without a default value are set to 1'bx. 2015-05-19 22:40:56 +02:00
entity_stream.cc vhdlpp: inout direction for ports. 2015-05-19 22:40:56 +02:00
expression.cc A VHDL ExpAttribute() can share the base so don't just delete them 2015-12-13 19:02:26 -08:00
expression.h vhdlpp: ExpUnary::elaborate_expr() elaborates its operand as well. 2015-08-09 18:48:15 +02:00
expression_debug.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
expression_elaborate.cc Spelling fixes 2015-08-17 11:34:58 -07:00
expression_emit.cc vhdlpp: NOT is translated to either ~(...) or !(...) depending on the argument type. 2015-06-24 23:53:32 +02:00
expression_evaluate.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
expression_stream.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
ivl_assert.h
lexor.lex vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
lexor_keyword.gperf
library.cc vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
library.h vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
main.cc Spelling fixes 2015-08-17 11:34:58 -07:00
package.cc vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
package.h vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
package_emit.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
parse.y VHDL-10: fix a compile warning and add some missing newlines 2015-12-19 10:50:42 -08:00
parse_api.h
parse_misc.cc
parse_misc.h vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
parse_types.h
parse_wrap.h
scope.cc vhdlpp: ExpName::probe_type() checks Subprogram parameters. 2015-06-24 23:53:33 +02:00
scope.h Spelling fixes 2015-08-17 11:34:58 -07:00
sequential.cc vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
sequential.h vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
sequential_debug.cc vhdlpp: 'wait on' and 'wait until' statements. 2015-06-08 18:42:52 +02:00
sequential_elaborate.cc vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
sequential_emit.cc vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
std_funcs.cc vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
std_funcs.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
std_types.cc vhdlpp: ScopeBase::is_enum_name checks enums from standard libraries. 2015-06-24 23:53:32 +02:00
std_types.h vhdlpp: ScopeBase::is_enum_name checks enums from standard libraries. 2015-06-24 23:53:32 +02:00
subprogram.cc vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
subprogram.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
subprogram_emit.cc vhdlpp: Procedure calls. 2015-06-24 23:53:32 +02:00
vhdlint.cc
vhdlint.h
vhdlnum.h
vhdlpp_config.h.in
vhdlreal.cc
vhdlreal.h
vsignal.cc vhdlpp: Allow initializers for variables. 2015-06-24 23:53:31 +02:00
vsignal.h vhdlpp: Allow initializers for variables. 2015-06-24 23:53:31 +02:00
vtype.cc vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00
vtype.h vhdlpp: VType::type_match() checks definitions provided by VTypeDef. 2015-06-24 23:53:33 +02:00
vtype_elaborate.cc
vtype_emit.cc vhdlpp: Fixed a problem with types defined as an array of arrays. 2015-08-09 16:43:04 +02:00
vtype_match.cc vhdlpp: VType::type_match() checks definitions provided by VTypeDef. 2015-06-24 23:53:33 +02:00
vtype_stream.cc vhdlpp: Refactored the way of handling standard types. 2015-06-24 23:53:32 +02:00

README.txt

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be:

  * yydebug | no-yydebug

  * entities=<path>

-L <path>
  Library path. Add the directory name to the front of the library
  search path. The library search path is initially empty.

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.

-w <path>
  Work path. This is the directory where the working directory is.


LIBRARY FORMAT:

The vhdlpp program stores libraries as directory that contain
packages. The name of the directory (in lower case) is the name of the
library as used on the "import" statement. Within that library, there
are packages in files named <foo>.pkg. For example:

    <directory>/...
       sample/...
         test1.pkg
	 test2.pkg
       bar/...
         test3.pkg

Use the "+vhdl-libdir+<directory>" record in a config file to tell
Icarus Verilog that <directory> is a place to look for libraries. Then
in your VHDL code, access packages like this:

    library sample;
    library bar;
    use sample.test1.all;
    use bar.test3.all;

The *.pkg files are just VHDL code containing only the package with
the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
statement, it looks for the <name>.pkg file in the <lib> library and
parses that file to get the package header declared therein.