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iverilog/tgt-vhdl
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Nick Gasson 2516d63805 A basic translation of the Verilog power operator to VHDL 
The exponentiation operator in VHDL is not defined for numeric_std
types. We can get around this by converting the operands to integers,
performing the operation, then converting the result back to the
original type. This will work OK in simulation but certainly will not
synthesise unless the operands are constant.

However, even this does not work quite correctly. The Integer type in
VHDL is signed and usually only 32 bits, therefore any result larger
than this will overflow and raise an exception. I can't see a way
around this at the moment.
 		2008-09-12 20:19:22 +01:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
cast.cc Fix vhdl_expr::cast when expression has no assigned type 2008-09-02 20:22:50 +01:00
configure.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
display.cc Avoid emitting empty string at end of $display translation 2008-09-06 13:23:55 +01:00
expr.cc A basic translation of the Verilog power operator to VHDL 2008-09-12 20:19:22 +01:00
logic.cc Handle BUFIF logic when vector inputs 2008-08-18 15:48:07 +01:00
lpm.cc Add IVL_LPM_CMP_GT 2008-09-02 19:07:38 +01:00
process.cc Use ivl_process_* functions for file/line number information 2008-08-02 10:44:03 +01:00
scope.cc Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
stmt.cc Use British spelling and fix a few typos 2008-09-09 19:57:32 +01:00
support.cc Support conversion of (un)signed to std_logic 2008-08-22 20:59:14 +01:00
support.hh Support conversion of (un)signed to std_logic 2008-08-22 20:59:14 +01:00
vhdl-s.conf Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
vhdl.cc Add (temporary) error for ICT_SCOPE_GENERATE 2008-09-06 11:38:37 +01:00
vhdl.conf Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_element.hh Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_helper.hh Handle '?' in vl_to_vhdl_bit 2008-08-11 13:53:42 +01:00
vhdl_syntax.cc A basic translation of the Verilog power operator to VHDL 2008-09-12 20:19:22 +01:00
vhdl_syntax.hh A basic translation of the Verilog power operator to VHDL 2008-09-12 20:19:22 +01:00
vhdl_target.h Avoid generating useless `wait for 0ns' statements 2008-08-05 11:02:36 +01:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00