luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/tgt-vhdl
History
Larry Doolittle 31d67fcd3e Enable -Wshadow by default 
The code base is almost shadow-free now, so this won't add much noise to the compiles.
Problems I know about:
 lxt{,2}_write.c:  patch sent upstream
 cflexor.c:  exposes gray area of name space boundary
 		2008-12-29 16:03:16 -08:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Enable -Wshadow by default 2008-12-29 16:03:16 -08:00
cast.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
display.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
expr.cc Avoid assertion failure in VHDL translate_select 2008-12-12 20:52:50 -08:00
logic.cc Spelling fixes 2008-09-09 19:21:42 -07:00
lpm.cc Fix part select of width-1 vector 2008-11-26 13:14:27 -08:00
process.cc Remove some uneccessary zero-time waits from VHDL outputs 2008-12-07 16:53:47 -08:00
scope.cc Add VHDL flag to specify maximum module depth 2008-12-16 09:05:33 -08:00
stmt.cc Make casex/z conditional x/z aware. 2008-12-18 16:32:08 -08:00
support.cc Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
support.hh Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
vhdl-s.conf Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
vhdl.cc Add VHDL flag to specify maximum module depth 2008-12-16 09:05:33 -08:00
vhdl.conf Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vhdl_config.h.in Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00
vhdl_element.cc Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_element.hh Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_helper.hh Handle '?' in vl_to_vhdl_bit 2008-08-11 13:53:42 +01:00
vhdl_syntax.cc Shadow reduction part 6 2008-12-29 16:00:03 -08:00
vhdl_syntax.hh Add VHDL flag to specify maximum module depth 2008-12-16 09:05:33 -08:00
vhdl_target.h Remove some uneccessary zero-time waits from VHDL outputs 2008-12-07 16:53:47 -08:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00