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iverilog/tgt-vhdl
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Nick Gasson 256454960c Add complete list of VHDL reserved words 
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.

(This code was already present, but the full list of reserved
words wasn't.)
 		2008-11-13 15:45:41 -08:00
..
vhpi Move the VHDL support package 2008-07-07 15:36:13 +01:00
Makefile.in Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
cast.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
configure.in
…
display.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
expr.cc Fix overly restrictive check for slices 2008-11-12 22:26:44 +00:00
logic.cc Spelling fixes 2008-09-09 19:21:42 -07:00
lpm.cc Fix IVL_LPM_MUX where inputs are different signedness to outputs 2008-10-05 17:08:19 +01:00
process.cc Use ivl_process_* functions for file/line number information 2008-08-02 10:44:03 +01:00
scope.cc Add complete list of VHDL reserved words 2008-11-13 15:45:41 -08:00
stmt.cc Shadow reduction part 4 2008-10-30 21:46:44 -07:00
support.cc Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
support.hh Tidy up reduction functions in support.cc 2008-09-13 18:20:12 +01:00
vhdl-s.conf Cary R.'s additional system functions, real value error messages, etc. 2008-09-06 12:06:01 +01:00
vhdl.cc Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-10-05 12:44:30 +01:00
vhdl.conf Remove redundant back-end selections. 2008-09-07 16:43:54 -07:00
vhdl_config.h.in
…
vhdl_element.cc Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_element.hh Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
vhdl_helper.hh Handle '?' in vl_to_vhdl_bit 2008-08-11 13:53:42 +01:00
vhdl_syntax.cc Add casex/z support 2008-10-14 20:16:10 +01:00
vhdl_syntax.hh Add casex/z support 2008-10-14 20:16:10 +01:00
vhdl_target.h Avoid generating useless `wait for 0ns' statements 2008-08-05 11:02:36 +01:00
vhdl_type.cc Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00
vhdl_type.hh Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00