iverilog/vhdlpp
Maciej Suminski 169228ad0f vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
..
Makefile.in vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
README.txt Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
architec.cc vhdlpp: Check generics when searching through constants. 2015-03-06 20:39:10 +01:00
architec.h Spelling fixes 2015-04-13 11:35:12 -07:00
architec_debug.cc updated FSF-address 2012-08-29 10:12:10 -07:00
architec_elaborate.cc vhdlpp: Minor code cleaning. 2015-06-08 18:42:52 +02:00
architec_emit.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
compiler.cc updated FSF-address 2012-08-29 10:12:10 -07:00
compiler.h vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration. 2014-10-01 14:56:32 +02:00
debug.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
entity.cc Fixed vhdlpp segfault if it processes an entity without any ports declared. 2014-08-04 20:27:21 -07:00
entity.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
entity_elaborate.cc vhdlpp: Fixed crash on unassociated generics. 2015-03-06 20:39:10 +01:00
entity_emit.cc vhdlpp: generics without a default value are set to 1'bx. 2015-05-19 22:40:56 +02:00
entity_stream.cc vhdlpp: inout direction for ports. 2015-05-19 22:40:56 +02:00
expression.cc vhdlpp: Support for selected assignments. 2015-06-24 23:53:31 +02:00
expression.h vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
expression_debug.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
expression_elaborate.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
expression_emit.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
expression_evaluate.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
expression_stream.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
ivl_assert.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
lexor.lex vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
lexor_keyword.gperf vhdlpp: Boolean values handled without using keywords. 2015-04-24 13:39:41 +02:00
library.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
library.h vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
main.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
package.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
package.h vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
package_emit.cc vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
parse.y vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
parse_api.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
parse_misc.cc vhdlpp: VTypeArray stores parent type, in case it is a subtype. 2015-02-04 16:57:43 +01:00
parse_misc.h vhdlpp: Minor cleaning, fixed copyright notices. 2014-08-25 17:29:35 +02:00
parse_types.h vhdlpp: Clone routines for Expression & VType classes. 2015-02-05 11:25:03 +01:00
parse_wrap.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
scope.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
scope.h vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody. 2015-06-24 23:53:31 +02:00
sequential.cc vhdlpp: 'wait on' and 'wait until' statements. 2015-06-08 18:42:52 +02:00
sequential.h vhdlpp: 'wait on' and 'wait until' statements. 2015-06-08 18:42:52 +02:00
sequential_debug.cc vhdlpp: 'wait on' and 'wait until' statements. 2015-06-08 18:42:52 +02:00
sequential_elaborate.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
sequential_emit.cc vhdlpp: 'wait on' and 'wait until' statements. 2015-06-08 18:42:52 +02:00
std_funcs.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
std_funcs.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
subprogram.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
subprogram.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
subprogram_emit.cc vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
vhdlint.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlint.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vhdlnum.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vhdlpp_config.h.in Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vhdlreal.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlreal.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vsignal.cc vhdlpp: Allow initializers for variables. 2015-06-24 23:53:31 +02:00
vsignal.h vhdlpp: Allow initializers for variables. 2015-06-24 23:53:31 +02:00
vtype.cc vhdlpp: VTypeArray::evaluate_ranges uses range boundaries to determine the direction. 2015-06-24 23:53:31 +02:00
vtype.h vhdlpp: Refactored the way of handling standard VHDL library functions. 2015-06-24 23:53:31 +02:00
vtype_elaborate.cc vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture. 2015-02-04 16:57:43 +01:00
vtype_emit.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00
vtype_match.cc Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
vtype_stream.cc vhdlpp: Support for time expressions. 2015-06-08 18:42:52 +02:00

README.txt

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be:

  * yydebug | no-yydebug

  * entities=<path>

-L <path>
  Library path. Add the directory name to the front of the library
  search path. The library search path is initially empty.

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.

-w <path>
  Work path. This is the directory where the working directory is.


LIBRARY FORMAT:

The vhdlpp program stores libraries as directory that contain
packages. The name of the directory (in lower case) is the name of the
library as used on the "import" statement. Within that library, there
are packages in files named <foo>.pkg. For example:

    <directory>/...
       sample/...
         test1.pkg
	 test2.pkg
       bar/...
         test3.pkg

Use the "+vhdl-libdir+<directory>" record in a config file to tell
Icarus Verilog that <directory> is a place to look for libraries. Then
in your VHDL code, access packages like this:

    library sample;
    library bar;
    use sample.test1.all;
    use bar.test3.all;

The *.pkg files are just VHDL code containing only the package with
the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
statement, it looks for the <name>.pkg file in the <lib> library and
parses that file to get the package header declared therein.