7fad4779c5
Add error recovery when elaboration of a type range fails.
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If elaboration of the msb or lsb expression in the range of a vector
type specification failed (due to an error in the Verilog code being
compiled), an assertion failure was being triggered when the compiler
attempted to evaluate the expressions. Bypassing the evaluation (and
using a default value) should allow us to recover from the error.
2014-10-30 20:42:12 +00:00
8ac06fb63f
Support vpiObjTypeVal for vec4Stack values.
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Also allow vpi_get_value outside of scope. (Return 'x)
2014-10-25 20:38:39 -07:00
4e727adc25
Merge branch 'master' into vec4-stack
2014-10-25 09:49:39 -07:00
3e9c14060f
lexor handles arbitrary length defines in the precompiled_defiles file.
2014-10-25 09:48:11 -07:00
702a8c3a05
Merge branch 'master' into vec4-stack
2014-10-24 15:17:31 -07:00
48d3972299
Remove a bunch of dead vvp opcodes.
2014-10-24 15:13:28 -07:00
62fce50f8c
Remove dead code for allocate_vec handling.
2014-10-24 13:07:53 -07:00
e4b862f3d1
Clean up vector handling dead code.
2014-10-24 11:17:36 -07:00
09d3a5de59
Port %pushv/str to vec4-stack style.
2014-10-24 10:16:35 -07:00
97bde47c31
Remove dead %set/dar and %set/dar/obj instructions.
2014-10-24 10:03:22 -07:00
1c80c6e37a
Remove dead stuff_ok_flags from draw_eval_vec4 functions.
2014-10-24 09:32:32 -07:00
4588f7c615
vec4 stack versions of queue pop methods.
2014-10-24 09:03:20 -07:00
006aef93d0
Fix a reference to an undefined element.
2014-10-23 16:56:13 -07:00
24b8752475
More cases where %store/prop/v takes a width.
2014-10-22 16:15:10 -07:00
3ddcf03764
Kill some eval_vec4.c warnings.
2014-10-22 13:01:25 -07:00
35f5d51028
Support testing nul for property that is an object.
2014-10-22 12:58:50 -07:00
87c019c65c
Merge branch 'master' into vec4-stack
2014-10-21 12:19:40 -07:00
69a1fecd2e
Handle arrays of object is comparison with null.
2014-10-21 11:47:22 -07:00
9964d67e5e
Implicit crop of vectors assigned to vector properties.
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The %store/prop/v takes a width so that it is guaranteed that
all assignments to a vector property will get the size right.
2014-10-21 11:46:59 -07:00
a98f21aa65
Merge branch 'master' into vec4-stack
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Conflicts:
elab_lval.cc
netmisc.cc
tgt-vvp/eval_object.c
tgt-vvp/vvp_process.c
vvp/codes.h
vvp/compile.cc
vvp/opcodes.txt
vvp/vpi_tasks.cc
vvp/vpi_vthr_vector.cc
vvp/vthread.cc
2014-10-21 09:12:02 -07:00
a63ca15735
Add support for putting a single delay from the VPI
2014-10-18 18:27:39 -07:00
d139142c29
Merge pull request #47 from orsonmmz/concat
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Expression concatenation in VHDL
2014-10-18 15:13:50 -07:00
af85d44d9f
Add support for putting three and six delays from the VPI
2014-10-17 20:06:01 -07:00
c5e0507941
Fix the modpath edge and vpi_put_delay() code
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The code to get the correct modpath delay for a given edge had the X and Z
entries swapped.
When putting a delay from the VPI the 2 delay to twelve delay mapping was
incorrect and the to/from X delays were also not being calculated correctly.
2014-10-17 19:42:55 -07:00
c55a013162
vhdlpp: Support for integer() function.
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Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd )
Real numbers are rounded, this is compatible with ModelSim behavior.
2014-10-17 14:53:59 +02:00
dfbca0b186
vhdlpp: Emit use_types in Architecture.
2014-10-17 14:13:06 +02:00
4a779f43bd
vhdlpp: Fix error message for 'right attribute.
2014-10-17 14:13:06 +02:00
97df6183a9
vhdlpp: Emit '-' std_logic value as 'x'.
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Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
f36bebf0e1
Remove some compile warnings.
2014-10-13 16:31:53 -07:00
3fd622e4eb
vlog95: Add support for emitting global tasks and functions
2014-10-13 09:51:55 -07:00
da4200c5bd
Update lz4 files to the latest from GTKWave
2014-10-13 09:44:57 -07:00
712f394224
Elaborate classes in packages.
2014-10-10 18:53:53 -07:00
d6685f40a1
Merge pull request #46 from orsonmmz/range
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VHDL attributes: 'range, 'reverse_range, 'left & 'right
2014-10-10 17:23:59 -07:00
9ff9cbf4aa
vhdlpp: Smarter determining the direction in for loops.
2014-10-10 18:39:14 +02:00
a992f3ce7c
vhdlpp: Evaluation for 'left and 'right attributes.
2014-10-10 18:35:17 +02:00
1a4edcac48
vvp: Accepts continuous assignment for 2-state nets.
2014-10-10 16:16:46 +02:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
7f6100be2a
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
2014-10-09 10:29:14 +02:00
4b60d2737e
vhdlpp: Skip signed & unsigned in types dump in packages.
2014-10-09 10:28:35 +02:00
c7beef907d
vhdlpp: Support for 'range and 'reverse_range attributes.
2014-10-08 11:18:06 +02:00
44da7de651
vhdlpp: prange_t may have the direction determined automatically.
2014-10-08 10:26:37 +02:00
6887c82540
vhdlpp: Added ExpAttribute::write_to_stream().
2014-10-08 10:21:03 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fddb3ec129
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.
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Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
2014-10-07 14:25:00 +02:00
bfafd175fa
Fix parse.y bad handling of file names in some situations.
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The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
2014-10-02 19:42:48 -07:00
23238aa7ac
Handle functions in $root scope.
2014-10-02 15:04:14 -07:00
2397aa1587
Merge pull request #45 from orsonmmz/subprogram
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Subprograms
2014-10-02 14:14:52 -07:00
Martin Whitaker
Stephen Williams
Cary R
Maciej Suminski