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8,478 Commits 23 Branches 234 Tags 41 MiB
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8478 Commits

Author SHA1 Message Date
steve 8a69c54886 elaborate complex l-values 2000-09-10 02:18:16 +00:00
steve b6ce313e91 move lval elaboration to PExpr virtual methods. 2000-09-09 15:21:26 +00:00
steve 3ae76a8638 initialize vlog info. 2000-09-08 17:08:10 +00:00
steve d86b37d90f Support unary + and - in constants. 2000-09-07 22:38:13 +00:00
steve e27934a577 ack, detect when lval fails. 2000-09-07 22:37:48 +00:00
steve ddcba9d91f The + operator now preserves signedness. 2000-09-07 22:37:10 +00:00
steve 44438c9678 more robust abut ternary bit widths. 2000-09-07 21:28:51 +00:00
steve 4cf75adf94 Fix bit padding of assign signal-to-signal 2000-09-07 01:29:44 +00:00
steve 49570b8cd9 encapsulate access to the l-value expected width. 2000-09-07 00:06:53 +00:00
steve 24e46723b0 Change elaborate_lval to return NetAssign_ objects. 2000-09-03 17:58:35 +00:00
steve e95d0c3b87 Properly ignore NetAssign_ objects. 2000-09-03 17:58:14 +00:00
steve ece3f5e0a2 Slightly more helpful warning. 2000-09-03 17:57:53 +00:00
steve 115d24a292 Pull NetAssign_ creation out of constructors. 2000-09-02 23:40:12 +00:00
steve ac81f6a201 Rearrange NetAssign to make NetAssign_ separate. 2000-09-02 20:54:20 +00:00
steve ff32325d07 t-dll iterates signals, and passes them to the 
target module.

 Some of NetObj should return char*, not string.
 2000-08-27 15:51:50 +00:00
steve eb781a7441 Handle out of range part select expressions. 2000-08-26 01:31:29 +00:00
steve 8876cda37f Get at gate information for ivl_target interface. 2000-08-26 00:54:03 +00:00
steve df113f962b Clean up warnings and portability issues. 2000-08-20 17:49:04 +00:00
steve d0fc6d515d Add ivl_target support for logic gates, and 
make the interface more accessible.
 2000-08-20 04:13:56 +00:00
steve 3cb666dd2f Add target calls for scope, events and logic. 2000-08-19 18:12:42 +00:00
steve a59bbdeb4f Proper error messages when port direction is missing. 2000-08-18 04:38:57 +00:00
steve 9abd84952b add th t-dll functions for net_const, net_bufz and processes. 2000-08-14 04:39:56 +00:00
steve 3ae4d2cf91 use -fPIC for sparc. 2000-08-12 20:54:33 +00:00
steve 534521f88b Limit signal scope search at module boundaries. 2000-08-12 17:59:48 +00:00
steve 566aad9e15 Start stub for loadable targets. 2000-08-12 16:34:37 +00:00
steve 248baa26e1 Move all file manipulation out of target class. 2000-08-09 03:43:45 +00:00
steve 91a462e38c Add the -N switch to the iverilog command. 2000-08-09 01:34:00 +00:00
steve d58533fd7b target methods need not take a file stream. 2000-08-08 01:50:42 +00:00
steve dab45178a7 Add vpi_vlog_info support from Adrian 2000-08-08 01:47:40 +00:00
steve e01137ced3 cleanup. 2000-08-02 14:48:15 +00:00
steve b5a36fef70 use bufif0 if z is in true case of mux. 2000-08-02 14:48:01 +00:00
steve 2e3e9ecf37 tri01 support in vvm. 2000-08-02 00:57:02 +00:00
steve 60c2046be6 Extend x or z that is top bit of a constant. 2000-08-01 22:44:26 +00:00
steve 1325a3e2b6 Use the iverilog command in documentation. 2000-08-01 21:32:40 +00:00
steve d677f226f3 Support <= in synthesis of DFF and ram devices. 2000-08-01 02:48:41 +00:00
steve eb93e3d2f5 Treat CR as white space in timespec lines. 2000-08-01 02:14:34 +00:00
steve 7cccbda275 Handle different forms of line end. 2000-08-01 01:38:25 +00:00
steve 931ec257f0 Report error when dumpfile is missing. 2000-07-31 03:34:31 +00:00
steve b6562d3ed9 timescale and min:typ:max expressions *do* work onw. 2000-07-30 22:09:09 +00:00
steve 0243fca8dc Rearrange task and function elaboration so that the 
NetTaskDef and NetFuncDef functions are created during
 signal enaboration, and carry these objects in the
 NetScope class instead of the extra, useless map in
 the Design class.
 2000-07-30 18:25:43 +00:00
steve 30a81731dd Introduce min:typ:max support. 2000-07-29 17:58:20 +00:00
steve 3aa250b16b Report code generation errors through proc_delay. 2000-07-29 16:21:08 +00:00
steve 39c71ef68a fix problem coalescing events w/ probes. 2000-07-29 03:55:38 +00:00
steve 4494a7a4f3 Support elaboration of disable statements. 2000-07-27 05:13:44 +00:00
steve 739365abe5 Parse disable statements to pform. 2000-07-26 05:08:07 +00:00
steve 880b712140 Get VCD timescale from design precision. 2000-07-26 04:07:59 +00:00
steve 08e6bf2e27 Make simulation precision available to VPI. 2000-07-26 03:53:11 +00:00
steve 5f7c298a21 Fix RAM matching. 2000-07-26 03:52:59 +00:00
steve 34399cf297 memory is not a data type in verilog. 2000-07-25 22:49:32 +00:00
steve cb7b1b6c94 Unlink z constants from nets. 2000-07-25 02:55:13 +00:00