27af95d402
Use perm_strings for named langiage items.
2004-02-18 17:11:54 +00:00
17e93b7cbe
Implement the wait statement behaviorally instead of as nets.
2003-05-19 02:50:58 +00:00
e941e7e805
Spelling fixes.
2003-01-30 16:23:07 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
91a755d0e8
Add support for memory words in l-value of
...
blocking assignments, and remove the special
NetAssignMem class.
2002-06-04 05:38:43 +00:00
bfad382fd1
Carry Verilog 2001 attributes with processes,
...
all the way through to the ivl_target API.
Divide signal reference counts between rval
and lval references.
2002-05-26 01:39:02 +00:00
5882c6a481
Redo handling of assignment internal delays.
...
Leave it possible for them to be calculated
at run time.
2002-04-21 22:31:02 +00:00
b094bbdcf4
Add support for conbinational events by finding
...
the inputs to expressions and some statements.
Get case and assignment statements working.
2002-04-21 04:59:07 +00:00
ab6c8cb4b8
Parser and pform use hierarchical names as hname_t
...
objects instead of encoded strings.
2001-12-03 04:47:14 +00:00
82831ea9a5
Use NetScope instead of string for scope path.
2001-11-22 06:20:59 +00:00
b6ce313e91
move lval elaboration to PExpr virtual methods.
2000-09-09 15:21:26 +00:00
24e46723b0
Change elaborate_lval to return NetAssign_ objects.
2000-09-03 17:58:35 +00:00
739365abe5
Parse disable statements to pform.
2000-07-26 05:08:07 +00:00
367db72c99
Add support for procedural continuous assignment.
2000-05-11 23:37:26 +00:00
44838f8973
Add support for force assignment.
2000-04-22 04:20:19 +00:00
b1fd927acb
Named events really should be expressed with PEIdent
...
objects in the pform,
Handle named events within the mix of net events
and edges. As a unified lot they get caught together.
wait statements are broken into more complex statements
that include a conditional.
Do not generate NetPEvent or NetNEvent objects in
elaboration. NetEvent, NetEvWait and NetEvProbe
take over those functions in the netlist.
2000-04-12 04:23:57 +00:00
2dd010dc04
Named events as far as the pform.
2000-04-01 19:31:57 +00:00
78ab1a7bba
Locate scopes in statements.
2000-03-11 03:25:51 +00:00
b734ecf02f
Macintosh compilers do not support ident.
2000-02-23 02:56:53 +00:00
a64a33e65a
Full case support
1999-09-29 18:36:02 +00:00
da4a7ea80a
assignment with blocking event delay.
1999-09-22 02:00:48 +00:00
b04148b754
Elaborate non-blocking assignment to memories.
1999-09-15 01:55:06 +00:00
8f68a07476
Add support for delayed non-blocking assignments.
1999-09-04 19:11:45 +00:00
6fb7120158
Parse non-blocking assignment delays.
1999-09-02 01:59:27 +00:00
6852a62e5a
procedural blocking assignment delays.
1999-07-12 00:59:36 +00:00
3ff6912bdd
Elaborate user defined tasks.
1999-07-03 02:12:51 +00:00
11b2b1740a
Handle expression widths for EEE and NEE operators,
...
add named blocks and scope handling,
add registers declared in named blocks.
1999-06-24 04:24:18 +00:00
853ad247a1
Elaborate and supprort to vvm the forever
...
and repeat statements.
1999-06-19 21:06:16 +00:00
fabb146342
Support case expression lists.
1999-06-15 05:38:39 +00:00
740c63291a
l-value part select for procedural assignments.
1999-06-13 23:51:16 +00:00
7605a7b1f0
Add parse and elaboration of non-blocking assignments,
...
Replace list<PCase::Item*> with an svector version,
Add integer support.
1999-06-06 20:45:38 +00:00
5de9b7c9f1
Parse and elaborate the concatenate operator
...
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
ce49708442
Parse OR of event expressions.
1999-04-29 02:16:26 +00:00
8bdd381cdf
Parse and elaborate the Verilog CASE statement.
1999-02-03 04:20:11 +00:00
fb439c78b9
Add the LineInfo class to carry the source file
...
location of things. PGate, Statement and PProcess.
elaborate handles module parameter mismatches,
missing or incorrect lvalues for procedural
assignment, and errors are propogated to the
top of the elaboration call tree.
Attach line numbers to processes, gates and
assignment statements.
1999-01-25 05:45:56 +00:00
6b2fa19429
Handle while loops.
1998-11-11 03:13:04 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve