Nick Gasson
|
404c22ac86
|
Improved implementation of $display
|
2008-06-20 11:51:13 +01:00 |
|
Nick Gasson
|
e0f41198d6
|
Blocking assignment working correctly
|
2008-06-18 13:49:03 +01:00 |
|
Nick Gasson
|
fb31a88c51
|
Blocking assignment nearly working
|
2008-06-18 13:30:19 +01:00 |
|
Nick Gasson
|
254ccb9ccb
|
First passing at blocking assignment
|
2008-06-18 13:06:27 +01:00 |
|
Nick Gasson
|
d2bebee9d9
|
Refactor before adding blocking assignment
|
2008-06-18 12:51:11 +01:00 |
|
Nick Gasson
|
af8c08e6a7
|
Allow optional VHPI $finish implementation
|
2008-06-17 20:16:16 +01:00 |
|
Nick Gasson
|
561953e494
|
Minial LPM to support continuous assignments
|
2008-06-16 19:41:01 +01:00 |
|
Nick Gasson
|
b8c1f9ab67
|
A system for linking ivl_signal_t to entities
|
2008-06-12 20:26:23 +01:00 |
|
Nick Gasson
|
a7cfdc3a87
|
Add VHDL if statement to AST types
|
2008-06-11 14:11:37 +01:00 |
|
Nick Gasson
|
1d28b935e8
|
Split vhdl_element.cc into multiple files
|
2008-06-08 13:27:48 +01:00 |
|
Nick Gasson
|
9f035108e1
|
Stub code for translating expressions
|
2008-06-04 14:59:04 +01:00 |
|
Nick Gasson
|
4bf2e1669d
|
Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
|
2008-06-04 13:52:56 +01:00 |
|
Nick Gasson
|
fe80da362c
|
Collect required packages as compilation progresses
|
2008-06-03 19:14:47 +01:00 |
|
Nick Gasson
|
4211e651d0
|
Stub file for processing statements
|
2008-06-03 18:26:36 +01:00 |
|
Nick Gasson
|
9292a087e8
|
Generate VHDL processes from Verilog processes
|
2008-06-02 16:17:01 +01:00 |
|
Nick Gasson
|
8189c4ee43
|
Generate VHDL entities and architectures for all module scopes
|
2008-05-31 15:28:25 +01:00 |
|
Nick Gasson
|
e38494a10c
|
Pretty-print VHDL output
|
2008-05-29 16:24:16 +01:00 |
|
Nick Gasson
|
bfa2bfc8ae
|
Makefile and autoconf changes to build VHDL code generator
|
2008-05-28 17:17:39 +01:00 |