dcc9b59f6d
Support SV [size] dimension for module and gate instances (issue #553 ).
...
Also output a proper error message if multiple dimensions are supplied
instead of failing an assertion.
2021-11-06 00:02:38 +00:00
dbf55da0f5
Clean up indentation.
2021-11-05 21:49:51 +00:00
ecbbb60fb6
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 16:55:03 +00:00
c34167b2c0
Fix detection of directly nested generate constructs.
...
If a generate construct is enclosed in a begin-end pair, it can't
be directly nested (1364-2005 section 12.4.2).
2021-08-04 10:37:26 +01:00
c7eaa06a2b
Add support for module input port default values (issue #489 ).
2021-03-10 08:21:42 +00:00
60a77b08d2
Add compiler and the start of vvp support for ->>
2021-02-19 23:21:51 -08:00
7bb8a4463f
Time literals need to be rounded using the time precision
2021-02-13 01:11:43 -08:00
18392a464d
Some clean up and add initial support for elaboration system tasks
2021-02-01 00:22:01 -08:00
d1eb4befcc
Add initial parsing for let construct
2021-01-18 13:06:44 -08:00
501586431b
Darrays are SV only and fix queue error message
2021-01-07 23:55:07 -08:00
5442f3fee7
Add sorry messages for missing array methods
2021-01-07 22:26:47 -08:00
89eabdfa35
Skip scalared and vectored keywords for packed arrays
2021-01-07 20:45:49 -08:00
32787bb973
Add support for SV edge
2021-01-07 01:22:49 -08:00
752401b88c
output ports of real type are variables, not wires.
2020-12-29 22:00:04 -08:00
16646c547c
Rework parsing of parameter types
...
Use the common data_type_or_implicit rules to support type
definitions for parameters. This eliminates a bunch of special
rules in parse.y, and opens the door for parameters having
more complex types.
2020-12-27 21:17:57 -08:00
5ca947ea8a
Allow signed/unsigned for fixed width integer data type parameters
2020-12-27 01:04:01 -08:00
156644d91e
Detect and complain about some constructor chain errors
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This.new is not allowed.
super.new beyond the first statement is not allowed.
And while I'm at it, clean up the use of "@" and "#" in
the code as tokens for this and super.
2020-11-22 15:31:40 -08:00
292d174cad
Add support for an empty ';' in the description text
2020-11-20 21:42:39 -08:00
b14a623eef
Update module items to include just a ';'
2020-11-20 20:48:55 -08:00
6880b39770
Refactor task declaration parsing and fix warning for empty port list.
...
1364-2005 and later allow a task declaration with an empty port list.
2020-10-03 09:30:51 +01:00
1064543d27
parse.y: Mark enum output ports always as IMPLICT_REG
...
Unless explicitly declared a wire an enum output port is of variable type
and should be marked as IMPLICT_REG.
Currently this is only done when the base type of the enum is `logic`. But
it should be done for all enums regardless of their base type.
Without this change for example the following snippet
```
typedef enum {
A,
B
} E;
module M (
input E ei,
output E eo
);
always_comb eo = ei;
endmodule
```
fails with the following error message
test_enum.sv:11: error: eo is not a valid l-value in M.
test_enum.sv:8: : eo is declared here as wire.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2020-09-20 19:14:28 +02:00
6ff07c1074
Enable support for providing a queue maximum index
2020-07-17 01:32:53 -07:00
07256646a5
Merge pull request #334 from purdeaandrei/f_fix_portless_declarationless_functions
...
Fix port-list-less declaration-less functions for SystemVerilog
2020-07-10 22:47:53 +01:00
c003bcc59a
Add support for <-> in constant and procedural contexts
2020-07-07 23:29:19 -07:00
018a649f59
A time variable defaults to unsigned, but can be declared as signed
2020-07-07 20:33:03 -07:00
a4d91c9023
Fix port-list-less declaration-less functions for SystemVerilog
...
For functions without a port list in parantheses, declarations are optional in SystemVerilog.
This is true even in IEEE1800-2005, but not in IEEE1364-2005
2020-06-22 23:51:10 +03:00
8b85064341
Fix GitHub issue 310 - improve port declaration error message.
2020-02-15 12:02:15 +00:00
b1114760fc
Fix for compatibility with old C++ standard.
2020-02-02 09:25:05 +00:00
33b822d997
Add support for local genvar declaration in generate loops.
...
As requested in GitHub issue #304 .
2020-01-31 20:29:22 +00:00
0023804777
Add support for increment/decrement operators in generate loop iteration.
...
As requested in GitHub issue #303 .
2020-01-30 21:45:04 +00:00
9f712429c8
Fix elaboration of void functions with no arguments (GitHub issue #281 )
...
N.B. commit 82c8a495#281 . It should have
referenced issue #280 .
2019-11-09 20:16:25 +00:00
06a60cac01
For SystemVerilog, support localparam in module parameter port lists.
2019-10-06 08:44:51 +01:00
befc91340c
Parse and elaborate unique and priority case statements
...
The unique, unique0, and priority keywords can decorate case statements
to tell the run time (or synthesis) to do extra tests (or make extra
assumptions). These tests are not implemented in the vvp run time, but
now the decorations make it to the code generators.
2019-10-05 16:23:04 -07:00
c86dc285cc
Fix for br1004 - fully support class construction in variable initialisation.
2019-10-05 20:10:11 +01:00
05641f386f
Add -g option to only enable supported assertion statements.
2019-10-05 13:37:03 +01:00
455702810e
Add support for parsing (and ignoring) the other unsupported SV assertions.
2019-10-05 08:55:11 +01:00
9167a236d8
Support import statements in packages and in the unit scope.
2019-10-03 19:44:44 +01:00
17f0dd7e6e
Enable package imports in blocks.
2019-10-01 09:07:59 +01:00
c5c264400e
Add support for package scope resolution for named events.
2019-10-01 09:07:54 +01:00
12fe4f2bf3
Fix handling of wildcard-imported types.
...
Don't add them to the explicit imports until they are referenced legally.
Stop searching when a matching name is found, even if it isn't a type name.
2019-10-01 09:07:48 +01:00
b0142a6406
Add support for named events in packages.
2019-10-01 09:07:39 +01:00
f69eccf903
Merge remote-tracking branch 'origin/master' into package-imports-rework
2019-10-01 09:06:15 +01:00
80478db6cc
Support typedefs in class definitions.
2019-09-30 08:07:56 -07:00
50d71c8512
Support for enumerations in classes.
2019-09-29 18:27:27 -07:00
03c4c63df1
Fix file/line reported for duplicate named blocks.
2019-09-27 22:19:30 +01:00
d3bced57cc
Correctly handle explicit and wildcard package imports.
...
Explicit imports should always conflict with local declarations using
the same name. Wildcard imports only conflict if they are referenced
before a local declaration with the same name.
This also unifies the detection of identifier conflicts.
2019-09-27 22:19:30 +01:00
823a508d6b
Implement SV immediate assertions.
2019-09-20 21:30:43 +01:00
02ee1c65d0
Support dynamic array initialisation in variable declarations.
2019-09-16 20:35:27 +01:00
832adc5c74
Improve handling of invalid packed and unpacked dimensions.
...
As reported on iverilog-devel on 2018-10-12, a dimension size of zero
could case the compiler to go into an infinite loop. Further tests
showed that unsized or queue dimensions entered as packed dimensions
would cause the compiler to crash.
2019-09-14 09:10:52 +01:00
e97883b1db
Fix for br1015 : assertion failure when task/function port is an array.
...
This is an error for Verilog and not yet supported for SystemVerilog.
2019-08-02 15:34:31 +01:00
Martin Whitaker
Cary R
Stephen Williams
Lars-Peter Clausen
Purdea Andrei