b69c4c9a2c
Fix range handling/checking and add a flag to allow deprecated port syntax.
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This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.
When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).
The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
2007-08-29 18:10:18 -07:00
ca924639a8
[PATCH] Better error message when an endmodule is missing (nested modules).
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This patch adds better checking for a missing endmodule or an attempt
to nest modules. A more descriptive message is printed and the location
of the original module definition is printed.
2007-08-28 17:49:34 -07:00
396ffd1cdd
Add support for conditional generate. In the process, fix bugs
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related to generate used multiple times by multiple scopes causing
spurious generation results.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-21 19:04:48 -07:00
ddd36ecb6c
Rework the heirarchical identifier parse syntax and pform
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to handle more general combinations of heirarch and bit selects.
2007-05-24 04:07:11 +00:00
f9c1c02f8d
Add support for -v flag in command file.
2007-04-19 02:52:53 +00:00
f621448ced
Parse edge sensitive paths without edge specifier.
2007-04-13 02:34:35 +00:00
c1c2381261
Parse all specify paths to pform.
2007-02-12 01:52:21 +00:00
0edb5a7547
Basic support for specify timing.
2006-09-23 04:57:19 +00:00
f001d0001a
Add support for generate loops w/ wires and gates.
2006-04-10 00:37:42 +00:00
77a0d7f4db
task/function ports can have types.
2006-03-30 05:22:34 +00:00
1021e5acc8
Fixes for stubborn compilers.
2005-12-05 21:21:18 +00:00
75ad90534b
Generalize signals to carry types.
2005-07-07 16:22:49 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
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of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
95c8115fc7
Add support for localparam ranges.
2004-08-26 04:02:03 +00:00
9949040285
Add support for the default_nettype directive.
2004-06-13 04:56:53 +00:00
5472b27e1f
Rewire/generalize parsing an elaboration of
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function return values to allow for better
speed and more type support.
2004-05-31 23:34:36 +00:00
e7fa56981a
More identifier lists use perm_strings.
2004-05-25 19:21:06 +00:00
413932e406
Verilog2001 new style port declartions for primitives.
2004-03-08 00:10:29 +00:00
177b6ffb6a
Addtrbute keys are perm_strings.
2004-02-20 18:53:33 +00:00
1295058e5d
parameter keys are per_strings.
2004-02-20 06:22:56 +00:00
27af95d402
Use perm_strings for named langiage items.
2004-02-18 17:11:54 +00:00
5b351599f0
Allow attributes on Verilog 2001 port declarations.
2003-07-04 03:57:18 +00:00
ccf4d4d7da
Module attributes from the parser
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through to elaborated form.
2003-06-20 00:53:19 +00:00
dc90f0d52d
Task/functions can have signed ports.
2003-06-13 00:27:09 +00:00
cb0a9b254e
More 2001 port declaration support.
2003-04-28 17:50:57 +00:00
561a268c9c
Break sized constants into a size token
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and a based numeric constant.
2003-04-14 03:37:47 +00:00
e58030498f
specparams as far as pform.
2003-02-27 06:45:11 +00:00
9adbdcb7c5
Add support for signed ports and nets.
2003-02-02 19:02:39 +00:00
e941e7e805
Spelling fixes.
2003-01-30 16:23:07 +00:00
46253ed873
Rework expression parsing and elaboration to
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accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
7e1e44e87a
Properly cast signedness of parameters with ranges.
2002-09-01 03:01:48 +00:00
4de141ab1d
Support parameters with defined ranges.
2002-08-19 02:39:16 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
28e0616543
Use standard name for iostream.
2002-06-06 18:57:18 +00:00
bfad382fd1
Carry Verilog 2001 attributes with processes,
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all the way through to the ivl_target API.
Divide signal reference counts between rval
and lval references.
2002-05-26 01:39:02 +00:00
700887d657
Verilog 2001 attriubtes on nets/wires.
2002-05-24 04:36:23 +00:00
e6c0629626
Add language support for Verilog-2001 attribute
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syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
74c219f171
Add ranges and signed to port list declarations.
2002-05-20 02:06:01 +00:00
bf10c5762a
Parse port_declaration_lists from the 2001 Standard.
2002-05-19 23:37:28 +00:00
361d4f2147
Drive strengths for continuous assignments.
2002-01-12 04:03:39 +00:00
c200c0c20e
Support integer for function return value.
2001-12-07 05:03:13 +00:00
ab6c8cb4b8
Parser and pform use hierarchical names as hname_t
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objects instead of encoded strings.
2001-12-03 04:47:14 +00:00
65f835f3eb
Properly parse net_decl assignments with delays.
2001-11-29 17:37:51 +00:00
4d0b840c26
Coerse input to inout when assigned to.
2001-11-10 02:08:49 +00:00
faa3a62259
detect module ports not declared within the module.
2001-10-31 03:11:15 +00:00
467ecf5b33
Error messages for missing UDP port declarations.
2001-10-21 01:55:24 +00:00
9f3e64e11a
Module types in pform are char* instead of string.
2001-10-21 00:42:47 +00:00
6466d02eda
Add automatic module libraries.
2001-10-20 23:02:39 +00:00
7a149a6943
Scope/module names are char* instead of string.
2001-10-20 05:21:51 +00:00
5dbea64759
Add support for signed reg variables,
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simulate in t-vvm signed comparisons.
2000-12-11 00:31:43 +00:00
Cary R
Stephen Williams
steve