d00e3fc9a9
Check IVL_LPM_MUX configuration.
2005-02-12 22:53:41 +00:00
6b7b82758a
Check nexus widths of IVL_LO_ nodes.
2005-02-12 06:17:43 +00:00
ee5bb5fcaf
Add the NetRepeat node, and code generator support.
2005-02-08 00:12:36 +00:00
97f83ffbe3
laborate reduction gates into LPM_RED_ nodes.
2005-02-03 04:56:20 +00:00
68a788221e
Support LPM_SUB
2005-01-30 05:09:04 +00:00
609b6a7baa
Netlist boolean expressions generate gate vectors.
2005-01-29 18:46:18 +00:00
7625a6c3e7
Check width of constant attached to nexus.
2005-01-29 16:47:52 +00:00
a5b431ad20
Show the lpm_mult device.
2005-01-28 05:36:18 +00:00
dfb7c7ba6f
Remove the NetEBitSel and combine all bit/part select
...
behavior into the NetESelect node and IVL_EX_SELECT
ivl_target expression type.
2005-01-24 05:28:30 +00:00
14f557e6f4
Check widths of ternary expressions.
2005-01-24 05:05:25 +00:00
cb4e0d4724
stub dump signed flags of magnitude compare.
2005-01-22 17:36:59 +00:00
a4710f375e
LPM_CMP_NE/EQ are vectored devices.
2005-01-22 16:22:13 +00:00
e28636776a
Change case compare from logic to an LPM node.
2005-01-22 01:06:55 +00:00
bf6a5d0f50
Implement LPM_COMPARE nodes as two-input vector functors.
2005-01-16 04:20:32 +00:00
9e94afe399
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 20:16:00 +00:00
8f2d679c8a
Unify elaboration of l-values for all proceedural assignments,
...
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
2004-12-29 23:55:43 +00:00
59566158c4
Better detail on event trigger and wait statements.
2004-12-18 18:55:08 +00:00
7973dad9f5
Arrange statement dumping in new source files.
2004-12-12 18:15:06 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
...
of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
e4ae832153
Clean up spurious trailing white space.
2004-10-04 01:10:51 +00:00
e45230061e
Dump tri0 and tri1 nets.
2004-09-25 01:57:33 +00:00
fca2e64808
Dump variable type of system function.
2004-06-30 03:05:04 +00:00
3dbc07f34d
Implement signed divide and signed right shift in nets.
2004-06-30 02:16:26 +00:00
b3529d8593
Help system function signedness survive elaboration.
2004-06-17 16:06:18 +00:00
bdc6cb8723
Dump NE LPM device.
2004-06-16 16:22:04 +00:00
973b4d9bcb
Pre-gcc3 compile error.
2003-12-03 04:27:10 +00:00
e56b77a43f
Add support for wait on list of named events.
2003-12-03 02:46:23 +00:00
9967bfcbfd
Handle erroneous event lists.
2003-12-03 01:54:07 +00:00
bfe31e22bf
Start handling pad of expressions in code generators.
2003-07-26 03:34:42 +00:00
bad861dba3
Module attributes make it al the way to ivl_target.
2003-06-23 01:25:44 +00:00
2a29c4fd62
Support real expressions in case statements.
2003-05-14 05:26:41 +00:00
3bd08e6212
Allow primitives to hvae unconnected input ports.
2003-05-13 01:56:15 +00:00
5d1d99a89f
Handle signed magnitude compare all the
...
way through to the vvp code generator.
2003-04-11 05:18:08 +00:00
d18934d444
Sign extend NetMult inputs if result is signed.
2003-03-29 05:51:25 +00:00
1222153cdf
Keep parameter constants for the ivl_target API.
2003-03-10 23:40:53 +00:00
258013f99f
Raw dump of double values for testing purposes.
2003-03-07 06:04:58 +00:00
d8706979ae
Eliminate use of ivl_lpm_name.
2003-02-25 03:39:53 +00:00
46253ed873
Rework expression parsing and elaboration to
...
accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
c2070777b2
The $time system task returns the integer time
...
scaled to the local units. Change the internal
implementation of vpiSystemTime the $time functions
to properly account for this. Also add $simtime
to get the simulation time.
2002-12-21 00:55:57 +00:00
9ce2806710
Fix synth2 handling of aset/aclr signals where
...
flip-flops are split by begin-end blocks.
2002-10-23 01:45:24 +00:00
166621bcb3
Generate vvp code for asynch set/reset of NetFF.
2002-09-26 03:18:04 +00:00
9c5ab36a8b
Fix switch case warnings.
2002-09-18 03:33:10 +00:00
75801a12e3
Display FF enables.
2002-09-16 00:28:25 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
693e9e5ad0
Store only the base name of memories.
2002-08-05 04:18:45 +00:00
a265ba2162
dump NOT gates.
2002-07-28 23:57:22 +00:00
4bac5c06ba
Dump l-value memory indices.
2002-06-05 03:43:14 +00:00
19d817503d
Offset lvalue index expressions.
2002-05-29 22:05:54 +00:00
422754f36f
Support carrying the scope of named begin-end
...
blocks down to the code generator, and have
the vvp code generator use that to support disable.
2002-05-27 00:08:45 +00:00
bfad382fd1
Carry Verilog 2001 attributes with processes,
...
all the way through to the ivl_target API.
Divide signal reference counts between rval
and lval references.
2002-05-26 01:39:02 +00:00
steve