e569e07d4e
vhdlpp: Type 'NATURAL' is translated to 'int unsigned'.
2015-02-19 17:07:41 +01:00
12b4914b63
vhdlpp: ExpName resolves enum values.
2015-02-17 10:15:57 +01:00
8a854affa6
vhdlpp: Clone routines for Expression & VType classes.
2015-02-05 11:25:03 +01:00
48265ecd9b
vhdlpp: Subprograms return types have their ranges evaluated if possible.
...
Added VTypeArray::evaluate_ranges() method.
2015-02-05 11:24:59 +01:00
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
90293d8e0a
vhdlpp: VTypeArray::is_variable_length() uses ScopeBase to determine if variable has constant length.
2015-02-04 16:57:43 +01:00
5d26f0e28d
vhdlpp: Added VTypeArray::is_variable_length() method.
2015-02-04 16:57:43 +01:00
774609fbbb
vhdlpp: VTypeArray stores parent type, in case it is a subtype.
2015-02-04 16:57:43 +01:00
b8b2f53027
vhdlpp: Added VType::get_generic_typename() method.
2015-02-04 16:57:43 +01:00
51b9191021
vhdlpp: Added VType::is_unbounded() method.
2015-02-04 16:57:42 +01:00
b05a19dffc
vhdlpp: VTypeArray emits dimensions in a bit smarter way.
2015-02-04 16:02:38 +01:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
9e856810b9
vhdlpp: Workaround to avoid translation of variables to wires in functions.
2014-09-30 15:59:45 +02:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
cb03802a17
vhdlpp: Added VTypeArray::basic_type() to cope with
...
arrays based on typedefs.
2014-09-15 12:10:05 +02:00
c98c3e5d14
vhdlpp: Inlined a few functions.
2014-09-15 12:10:04 +02:00
a63289c2fc
vhdlpp: VTypeArray::range_t handles direction (to/downto).
2014-09-15 12:10:04 +02:00
94caa4881e
vhdlpp: Added VTypeEnum::write_to_stream().
2014-09-15 12:10:04 +02:00
0f728b9150
vhdlpp: Minor cleaning, fixed copyright notices.
2014-08-25 17:29:35 +02:00
b0c79d5d1c
vhdlpp: Added VType::emit_name() that skips emission of a name if it is empty (otherwise '\' is outputted).
2014-08-25 17:05:15 +02:00
150fe088a6
vhdlpp: VTypeRecord is marked as acceptable in packed arrays. VTypeDef is accepted depending on the base type.
2014-08-25 16:56:46 +02:00
27730395ca
vhdlpp: Type of an array is selected depending on the element type.
2014-08-22 10:49:55 +02:00
8e9c25a23e
vhdlpp: Added 'packed' property for VTypes.
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It detetermines if a type can be used as the base type of a packed array.
2014-08-22 10:45:02 +02:00
69b145e216
Minor cleaning for valgrind output.
2014-08-06 15:01:28 +02:00
5ed60a151f
Added support for real type in vhdlpp.
2014-08-06 15:00:35 +02:00
d6b6b76015
Update header files to use a more standard name to prevent rereading
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This is from github report #16 . There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
8487cb5616
Do a better job of figuring the vtype of an expression.
2013-06-12 14:21:36 -07:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
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We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
d9fea802da
Function declarations in packages
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This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
5651e6e001
Improve error handling.
2012-11-02 19:30:12 -07:00
85e000ed0c
Handle prefix expressions that include array index expressions.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
621c09105c
Sort the typedef emits so that types are emitted in the order used.
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It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
2012-05-22 17:31:27 -07:00
369a0b9eca
VHDL named types work in more places.
2012-05-22 17:31:27 -07:00
4748f0cb5e
Handle incomplete type declarations
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Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
2012-05-22 17:31:27 -07:00
039e6014fe
Rework VType::emit_def methods / use packed arrays to implement arrays.
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VHDL arrays are more like SV packed arrays, so use packed arrays
to implement them.
2012-05-22 17:31:26 -07:00
021d944a30
Probe type of ExpName with a record prefix.
2012-05-22 17:31:25 -07:00
79435924f2
Move some VType::show methods to ::write_to_stream methods.
2012-05-22 17:31:25 -07:00
9ed56a6354
Parse record types, and some new aggregate types.
2012-05-22 17:31:25 -07:00
84f14dbc81
Spelling fixes to vhdlpp tree
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Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
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Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
6268db6e68
Handle simple type declarations.
2011-10-09 15:25:35 -07:00
30cfcbe2dc
Rework elaborate/emit of types.
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This rework is needed to reasonably handle new types, like enums.
2011-10-02 10:56:00 -07:00
271aaf6376
Parse enumeration type declarations.
2011-10-01 17:04:04 -07:00
116d9f5f54
Merge branch 'master' into work7
2011-07-24 11:06:22 -07:00
46684bb28e
Use dynamic allocation for VHDL global built-in types
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Instead of using automatic variables for global
types, I allocate them dynamically. Thanks to it,
all type objects can be treated in the same way,
as all of them are pointers allocated with `new'.
Now we will be able to remove all scopes in the same
manner, no matter if it is a global or local scope,
by deleting all carried pointers.
2011-07-24 09:45:25 -07:00
38854822da
Write package headers to a library file
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Build up a work library by writing a VHDL representation of the
package header into a source file. This representation needs to
be accurate enough that later invocations of vhdlpp can read them
with the VHDL parser.
2011-07-19 19:19:27 -07:00
a53082176d
Arrange for ports used as l-values to be declared as "reg".
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Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
2011-05-15 16:17:51 -07:00
Maciej Suminski
Cary R
Stephen Williams
Arun Persaud
Larry Doolittle
Pawel Szostek