Commit Graph

7283 Commits

Author SHA1 Message Date
Stephen Williams c7c10613d7 blif support for unsigned magnitude comparison. 2013-08-01 17:28:04 -07:00
Stephen Williams dfc44db0ef BLIF support for IVL_LPM_CMP_EQ and IVL_LPM_CMP_NE 2013-08-01 17:28:04 -07:00
Stephen Williams 7a6192b5c8 Generate blif code for IVL_LPM_SUB device. 2013-08-01 17:28:04 -07:00
Stephen Williams 05f90bcf55 Support blif emit of IVL_LPM_ADD device. 2013-08-01 17:28:04 -07:00
Stephen Williams 1be59d8ae7 Add blif target to RPM package. 2013-08-01 17:28:04 -07:00
Stephen Williams b4dbb81af7 Fix handling of certain constants in ivl_target.h API.
The construction of the ivl_design_t consts member was broken,
not properly handling the addition of new objects.
2013-08-01 17:28:04 -07:00
Stephen Williams e709849243 Add a README-BLIF.txt file for the blif target. 2013-08-01 17:28:04 -07:00
Stephen Williams 1b2fa39cdc Add some more basic logic gates to blif target. 2013-08-01 17:28:04 -07:00
Stephen Williams b4ec36ec78 blif nex_data_t collects name data early.
It is possible for the get_name_index() method to be called before
the get_name() method, so need to handle that case.
2013-08-01 17:28:04 -07:00
Stephen Williams dddaacc6fd Follow non-canonical bit numbering.
The signal bit numbering should be used for signals. This is
necessary for .model ports because the user specified numbers
are part of the interface, but once that is done, it is trivial
to follow it internally as well.
2013-08-01 17:28:03 -07:00
Stephen Williams e0c9efd129 Implement blif support for constants and some logic/lpm gates.
This starts the handling of various logic gates.
2013-08-01 17:28:03 -07:00
Stephen Williams 01b81e0dbc Implement the ivl_target ivl_scope_child functions.
These are a more convenient way of iterating through child scopes.
2013-08-01 17:28:03 -07:00
Stephen Williams d2034a6458 Initial BLIF code generator.
Add the -tblif code generator target, and include some basic
useful behavior.
2013-08-01 17:28:03 -07:00
Cary R c4edbda969 Warn that the SystemVerilog array querying functions are not supported. 2013-07-31 19:40:25 -07:00
Cary R f3917778bc vlog95: Add some support for $signed()/$unsigned() in a CA 2013-07-29 10:26:56 -07:00
Cary R 032f12af45 Fix some sign information in the CA code. 2013-07-29 10:26:49 -07:00
Cary R bb37b74f98 Fix for br884 (packed array access problems) 2013-07-28 13:24:57 -07:00
Cary R 817a38494c vlog95: add support for zero argument functions and better named block detect
Add support for translating a zero argument function by adding a dummy
argument and improve the code that looks for a named block in a process.
2013-07-24 19:41:59 -07:00
Cary R d6fe6ea936 Add support for calling a user functions as a task (SV) 2013-07-24 19:38:00 -07:00
Cary R af48acca14 Update tgt-pcb make clean target to remove lex/yacc generated file. 2013-07-22 10:30:39 -07:00
Cary R 11696e23d1 vlog95: Add support for translating a SV function return statement 2013-07-19 10:52:54 -07:00
Cary R 8b7dde0e41 vlog95: improve parameter select warning. 2013-07-18 17:44:45 -07:00
Cary R 54cb85adfc Add support for a generate scope to vvp and the vpi routines.
Instead of just translating a generate scope to a named begin/end scope
this patch creates a generate specific scope (vpiScopeGenerate) that is
of the vpiGenScope type. This may not match the standard 100%, but does
allow the FST dumper to denote generate scopes differently than the
other scope types. Most of the VPI code treats a vpiGenScope just like a
named block so only the FST dumper should have different behavior.
2013-07-17 10:57:02 -07:00
Cary R f636ffde48 Update some line numbers in the cppcheck suppression files 2013-07-16 11:27:37 -07:00
Cary R 87235b618b Update FST files to latest from GTkWave 2013-07-16 11:27:23 -07:00
Cary R e4cc12f3b9 Remove old comment and enclose sizeof value in parenthesis (vvp_vector8_t) 2013-07-12 10:57:39 -07:00
Cary R 9d1084d3c0 Remove reentrant support from tgt-pcb parsing
This is just extra overhead since the pcb target does not call the scanner
recursively. This also removes some compile warnings.
2013-07-11 19:19:22 -07:00
Cary R 21b24c7725 Fix more compile warnings and a minor bug 2013-07-11 19:10:25 -07:00
Cary R 3e75f8e41f Remove a compile warning 2013-07-11 18:03:00 -07:00
Cary R dec0fa622c Add CXX warning flag to tgt-pcb and tgt-vhdl and fix warnings 2013-07-11 17:40:57 -07:00
Cary R dbd05557ca Fix Makefile and scope.cc in tgt-pcb 2013-07-09 18:54:50 -07:00
Cary R e30334e527 Add ivl_parameter_width() function to ivl interface 2013-07-09 18:22:40 -07:00
Cary R 3e76f6d656 vlog95: more procedural $signed()/$unsigned() support
Add support for detecting when to add a $signed() or $unsigned() to
create a self-determined context. This makes the test in the test suite
pass, but there could still be issues
2013-07-09 17:55:21 -07:00
Cary R 91ad8a72c6 vlog95: Keep the scaling for a variable parameter indexed part select
The select expression scaling needs to be kept for a variable indexed
part select of a parameter since parameters are zero based in 1364-1995.
2013-07-05 17:23:28 -07:00
Cary R e2361fab29 vlog95: Better unsupported select warnings and variable parameter bit select
Since parameters are now passed by reference use that information to print
the parameter name in a select vs trying to figure it out by searching the
scope looking for a parameter with the same file, line and value information.

Only print the $signed() may need to be removed messages for a select
expression that will actually be cast to signed.

Use the actual parameter information to warn that -pallowsigned=1 is needed
for a parameter when the LSB > MSB.
2013-07-05 16:31:05 -07:00
Cary R f6b8d613ab Fix space issue. 2013-07-05 16:20:48 -07:00
Cary R 3a3cd8565d Add elaborate_expr_param_bit_ and pass param refs for variable selects
For variable parameter selects (indexed and bit) pass the value being
selected as a parameter reference instead of just a numeric constant
so it is easy to get the underlying parameter information.

Move the parameter bit select code into its own routine and cleanup
the remaining general code.

This should not effect the VVP code, but the ivl_expr_parameter(<expr>)
routine can be used to get at the actual parameter information in the
vlog95 target.
2013-07-05 16:16:54 -07:00
Cary R b9bcacd803 Update ivl.def file to include new routines and one missing routine
Add the new ivl_parameter routines (lsb, msb, signed) and add the
missing definition for ivl_parameter_scope.
2013-07-05 10:41:51 -07:00
Cary R cbd1b948a2 vlog95: emit an entire parameter reference by name instead of value. 2013-07-05 10:35:31 -07:00
Cary R d1c1997acf Add missing file/line information for a full parameter reference. 2013-07-04 16:50:26 -07:00
Cary R fcbb41c391 vlog95: Get sign info correct for procedural power to shift conversion 2013-07-04 14:33:39 -07:00
Cary R e736c022b1 Merge branch 'master' of github.com:steveicarus/iverilog 2013-07-04 11:30:02 -07:00
Cary R d08e0270e4 Add support for getting parameter MSB, LSB and sign from the ivl interface 2013-07-04 11:29:25 -07:00
Stephen Williams bb1d26f4f7 Fix warning/error finding static properties. 2013-07-03 20:07:58 -07:00
Stephen Williams 173577d5f7 Merge branch 'work14' 2013-07-03 20:00:22 -07:00
Stephen Williams 5326790932 Add support for class static properties.
Static properties are like variables in a named scope.
Detect these variables during elaboration so that the
code generator just sees them as variables.
2013-07-02 20:16:47 -07:00
Stephen Williams 4ef3ac5ca6 Implement const properties of classes.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
2013-07-02 20:16:47 -07:00
Stephen Williams cf47a759d1 Implement the "local" class member protection.
Test during elaboration that the member really is
accessible in the context where the elaboration
happens.
2013-07-02 20:16:47 -07:00
Stephen Williams 046535cfbb Blend implicit constructor with explicit constructor
Class types that have both implicit construction and
an explicit constructor can blend the implicit and
explicit construction into the "new" function defined
by the user. This doesn't change the behavior any, but
removes a function call and related scope.
2013-07-02 20:16:47 -07:00
Stephen Williams 637d43fb5a Add support for logic vector properties in classes.
This is similar to but not the same as bit(bool)
vector properties in classes.
2013-07-02 20:16:47 -07:00