Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
This patch set covers C code, with the notable exception of
vpi/lxt_write{,2}.c.
This patch cleans up the Makefile.in files.
We only need to delete config.log in the lower directories.
We reference the *.in files at $(srcdir)/
We need to make distclean for the tgt-(fpga,pal,verilog) directories.
This is to cleanup the Makefile.
Add some missing "rm -r f dep"
Collapse all the configure checks to a single configure script in
the root of the source tree. This makes the configure process run
a lot faster, expecially on Windows systems that are slower in general.
Remove the #ident and $Log$ strings from all the header files and
almost all of the C/C++ source files. I think it is better to get
this done all at once, then to wait for each of the files to be
touched and edited in unrelated patches.
The power operator is different in that it uses the signed version
if either of it's arguments are signed. This patch fixes the code
generator to do this correctly.
This patch makes the code generator put the compiler version
information in the vvp output file. It also adds checks in vvp
to verify that this version is compatible with the run time.
I am assuming that a base release 0.9.0, etc. will have a
blank VERSION_TAG. Any change relative to the release will have
a VERSION_TAG.
It is ot uncommon for the arguments to logical or to leave stuff
in bit registers 4-7. Allow the lor itself to take advantage of
that to save some %mov instructions.
When padding expressions, pre-allocate the target space and calculate
the sub-expression directly into the target. Then pad from there. This
saves a move into the result space.
This patch updates the GNU address in the -V output, adds the
VERSION_TAG info to the tgt-vvp back end and adds the whole -V
hook to the tgt-vhdl back end.
In a procedural single bit non-negated reduction (&, | or ^)
we need to translate a 1'bz to a 1'bx. The easiest way to do
that is with two %inv opcodes. This patch modifies the code
generator to do this for this very special case.
This configure option causes the installed commands to have
a suffix string that makes them distinct from other versions
that also have a suffix string. This allows for multiple
installed versions of Icarus Verilog.
Also, move installed C/C++ header files into a subdirectory of
their own under the target include directory, to make clearer
the purpose and source of those files.
In the vvp code generator, when zero/sign extending a sub-expression,
the sub-expression is first evaluated and stored in one location in
the thread vector store, then is copied and extended into a second
location. The storage used for the initial sub-expression evaluation
is never deallocated.
This patch fixes a number of problems related to the divide and
modulus operators.
The net version (CA) of modulus did not support a signed version.
Division or modulus of a value wider than the machine word did
not correctly check for division by zero and return 'bx.
Fixed a problem in procedural modulus. The sign of the result is
only dependent on the L-value.
Division or modulus of a signed value that was the same width as
the machine word was creating an incorrect sign mask.
Division of a signed value that would fit into a single machine
word was not checking for division by zero.
Division or modulus of a wide value was always being done as
unsigned.
Added a negative operator for vvp_vector2_t. This made
implementing the signed wide division and modulus easier.
Support arrays of realtime variable arrays and net arrays. This
involved a simple fix to the ivl core parser, proper support in
the code generator, and rework the runtime support in vvp.
Even on 64 bit machines immediate values should be limited to
32 bits so that the a.out file will run correctly on a 32 bit
machine. This patch fixes a number of places where the code
generator was not checking for/observing this.
This patch adds non-blocking event control for array words.
It also fixes a problem where the word used to put the
calculated delay for a non-blocking array assignment was
not being released. It also fixes the non-blocking array
assignments to correctly handle off the end/beginning part
selects.
Since some event control assignments can be skipped we need an
event control clear so that future %evctl statements do not fail
their assert. This patch adds %evctl/c and uses it in the compiler
as appropriate to keep the event control information in sync.
This patch adds full event control for vectors and parts of a
vector. It also fixes the other non-blocking part select code
to correctly handle a negative offset ([1:-2] of a [4:0] will
have an offset of -2).
When evaluating an expression into an index register bit 4 is used
to determine if the expression had any X/Z bits. In the case of a
constant immediate value this can not happen so make sure the bit
is cleared.
We need consistent pointer output (%p) and under MinGW we need to
us _snprintf instead of snprintf to get this. The recent event
control addition missed this. This has been reported to the MinGW
developers and they are working on a solution.
This patch pushes the non-blocking event control information to
the code generator. It adds the %evctl statements that are used
to put the event control information into the special thread
event control registers. The signed version (%evctl/s) required
the implementation of %ix/getv/s to load a signed value into
an index register. It then adds %assign/wr/e event control based
non-blocking assignment for real values. It also fixes the other
non-blocking real assignments to use Transport instead of inertial
delays.
When the -V flag is passed to the iverilog command, we can easily
print the version information for the driver itself, but it is also
valuable to probe all the components that would have been used for
a real compile. So the driver executes the preprocessor and the ivl
core to have them print version information.
The ivl core program also tries to load the target code generator
and get version information to print. For this to work, create a new
optional entry point "target_query" that takes a query key string as
an argument and returns a const string as the result. Use this with
the key "version" to get version information out of the target.
Target selection is done by the DLL target code generator, so there
is no value having a layer of target selection ahead of it. Remove
all that redundant code and simplify the target config files to reflect
this.
It is possible for signe-extend to have a delay attached to it. (Same
for repeat.) Handle it like other LPM devices, by stuffing a .delay
device into the output path of the device, if appropriate.
Nothing to do with tab width! Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings. No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.
Low priority, simple entropy reduction. Please apply
unless it deletes some steganographic content you want
to keep.
This patch adds blocking repeat event controls and also makes the
base repeat statement sign aware. If the argument to repeat is
negative (it must be a signed variable) then this is treated just
like an argument of 0 (there is no looping). Doing this allows us
to model the repeat event control as follows.
lhs = repeat(count) @(event) rhs;
is translated to:
begin
temp = rhs;
repeat (count) @(event);
lhs = temp;
end
This patch also pushes the non-blocking event control
information to the elaboration phase where it will report they
are not currently supported.
Be more sophisticated with the code generated for constant values.
When values are large, use an optimal mix of %movi and %mov
instructions to get the desired value, no matter what the content.
This patch pushes the automatic property for both tasks and
functions to the code generators. The vvp back end does not
currently support this so it will error out during code
generation. The VHDL back end should be able to use this
property and tgt-stub prints the property. Having this will
also make it easier when we do adding this to the runtime.
This patch fixes a bug in the VVP code generator that causes syntactically
incorrect code to be generated if an event expression contains a memory or
array port.
This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().
Also document the new statements.
This handles the general case of a non-real operand to a real-valued
division. This can turn up if only 1 operand of a divide is real. In
this case the division as a whole is real and the other operand must
be cast to real.
This method creates an extra node, but it should be a very compact
node and this node does no evaluation tricks so in the run time should
be no more expensive then folding the cast into the .arith/div.r itself.
The load-and-add for vectors %load/vp0/s can be combined with the
load-and-add for array words, and the %load/avp0/s added to round
out the combinations. This can make for fewer instructions when
words are padded in arithmetic expressions.
The %load/vp0 instruction adds a signed value to the signal value being
loaded, but it doesn't allow for a signed source vector. Add the
%load/vp0/s instruction that pads the loaded vector, and add the code
generator details to properly use it.
Actually, the immediate value handling is a little chaotic and should
be cleaned up. This patch opens the door for allowing signed immediate
values, and uses them in a few places where they are explicitly handled.
We must go through the opcodes that can take immediate values and make
explicit whether they are signed/unsigned/etc, and what their size
limits are.
The part select of a vector is converted by the compiler during
elaboration to a 0-based canonical address. But since it is legal
to address bits below the LSB, the canonical address can be negative.
So make the part select base for selecting from signals work with
signed arithmetic and make the code generator generate negative
indices when needed.
This is not a solution to all the problems, but is a better catch-all
then what is currently there. Allow the index field to be a T<> that
accesses the thread to get the address index.
Note that the lexor.lex currently returns the T<> as a T_SYMBOL, and the
users of T_SYMBOL objects need to interpret the meaning. This is
probably not the best idea, in light of all the other *<> formats that
now exist.
Fold the bi-directional part select into the pass switch (tran) support
so that it can be really bi-directional. This involves adding a new
tranvp device that does part select in tran islands, and reworking the
tran island resolution to handle non-identical nodes. This will be needed
for resistive tran devices anyhow.
The draw_net_input function is modified to account for nexus that is
a port of an island. Draw the ports (and the islands if necessary)
to the island and use the port output for the nexus instead of the
port input. This allows the bi-directional behavior of the port to
interpose itself in the data flow.
In this process of these changes, the draw_net_input function was
reorganized, and all the considerable amount of code for it was
moved to a file of its own. (vvp_scope.c is pretty unruly.)
The handling of immediate add used to do 16bits at a time. When it went
up to 32bits, the need to work in chunks vanished, but the chunk handling
was still there, this time shifting by 32, which causes problems on 32bit
machines. Simplify the %addi handling to avoid this.
Clarify that operands are typically 32bits, and have the code generator
make better use of this.
Also improve the %movi implementation to work well with marger vectors.
Add the %andi instruction to use immediate operands.
The MinGW system() implementation appears to return the straight
return value instead of the waitpid() like result that more
normal systems return. Because of this just return the system()
result without processing for MinGW compilations.
Older version of the MinGW runtime (pre 3.14) just used the
underlying vsnprintf(). Which has some problems. The 3.14 version
has some nice improvements, but it has a sever bug when processing
"%*.*f", -1, -1, <some_real_value>. Because of this we need to use
the underlying version without the enhancements for now.
snprintf prints %p differently than the other printf routines
so use _snprintf to get consistent results.
Only build the PDF files if both man and ps2pdf exist.
MinGW does not know about the z modifier for %d, %u, etc.
Add some missing Makefile check targets.
Array words don't have a vpiHandle with a label, so the %vpi_call
needs a special syntac for arguments that reference array words.
This syntax creates an array word reference that persists and can
be used at a VPI object by system tasks.
Memory words may have part selects assigned, but the code messed up
the testing for the validity of the part select base. This fixes do
detect constant bases so that base validity tests are handled at
compile time.
The draw_input_from_net function was being used to access words of
a var array, which doesn't work. Have the draw_input_from_net punt
on that case, and by the way the mux inputs don't need to use that
function, instead they should use the general draw_net_input function
to get the input labels.
It is possible for an array to have 1 word in it, so using the array
count to detect an array is incorrect. Use the ivl_signal_dimensions
function, which is there exactly for that purpose.
Save tons of space per memory word by not creating a vpi handle for
each and every word of a variable array. (Net arrays still get a
vpiHandle for every word.) The consequence of this is that all
accesses to a variable array need to go through the indexing.
This commit handles the most common places where this impacts, but
there are still problems.
It is a quirk of the $signed() system function that the argument
is converted to signed, but the operation that is performed is
not changed. So arithmetic operators on unsigned arguments inside
a $signed() expression still perform unsigned arithmetic.
The abs() function needs to be able to turn -0.0 into 0.0. This proved
to be too clunky (and perhaps impossible) to do with tests and jumps,
so add an %abs/wr opcode to do it using fabs().
The min/max functions need to take special care with the handling
of NaN operands. These matter, so generate the extra code to handle
them.
This patch adds file and line information for parameters and
local parameters. It also adds file/line stubs for signals in
the tgt-* files. It adds the pform code needed to eventually
do genvar checks and passing of genvar file/line information.
It verifies that a genvar does not have the same name as a
parameter/local parameter.
Implement in behavioral the abs/min/max operators for real values.
The parser treats these builtin functions as operators, unary or
binary, and elaborates them appropriately.
Also add enough code generator support to handle real valued expressions
in thread context.
This patch adds code to push the file and line information
for scope objects (modules, functions, tasks, etc.) to the
runtime. For modules, this includes the definition fields.
This patch adds ifnone functionality. It does not produce an
error when both an ifnone and an unconditional simple module
path are given. For this case the ifnone delays are ignored.
When generating a real expression you can have bits of the
expression that use vector only operands. When this happens
evaluate that part of the expression as a vector and then
convert it to a real value.
Detect thread bit allocation failures and fail gracefully. Print an
error message that points at the expression in question, and return
with an error code so that the compiler exits with an error.
This patch adds the ability to assign/deassign a bit or part select.
It also cleans up the code and fixes some problem in the forcing of
strength aware nets.
This patch adds a %assign/av/d opcode. This is a version of %assign/av
that allows a delay expression. Ultimately this allows a dynamically
indexed array to have a delay expression (non-constant delay value).
This patch removes the overly optimistic lookaside save for a signal
that has been set (%set/v). This is incorrect because if a force or
assign are active the value will not be set as expected.
Larry Doolittle
Cary R
Stephen Williams
Martin Whitaker
Martin Whitaker