Nick Gasson
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0a8fd50c4a
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Find assignments that could be initializers
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2008-06-13 13:59:48 +01:00 |
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Nick Gasson
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0df3eabe26
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Convert `if (foo) ..' to `if foo = '1' then ..'
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2008-06-12 11:36:21 +01:00 |
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Nick Gasson
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8fe2211e2b
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Generate `after' modifier instead of `wait' statements
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2008-06-12 11:24:43 +01:00 |
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Nick Gasson
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7eb41304e6
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Generate rising/falling edge detectors
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2008-06-12 10:36:38 +01:00 |
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Nick Gasson
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a7cfdc3a87
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Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
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Nick Gasson
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b010b8e3ca
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Use `assert false' as initial translation of $finish
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2008-06-11 13:37:21 +01:00 |
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Nick Gasson
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26a2c69c2e
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Change architecture name to `FromVerilog'
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2008-06-11 11:31:43 +01:00 |
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Nick Gasson
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5a7cfd8c02
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Clean up vhdl_comp_inst
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2008-06-10 14:00:15 +01:00 |
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Nick Gasson
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babe694366
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Generate port mappings
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2008-06-10 13:58:41 +01:00 |
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Nick Gasson
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f6753a9013
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Add ports to component declarations
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2008-06-10 11:24:16 +01:00 |
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Nick Gasson
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3106fe0ed6
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Generate port declarations for entities.
But doesn't emit them yet!
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2008-06-09 16:27:04 +01:00 |
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Nick Gasson
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3b5d56e087
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Allow n-ary expressions
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2008-06-09 14:53:50 +01:00 |
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Nick Gasson
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aa91186119
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Add AST elements for unary/binary expressions to model logic gates
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2008-06-09 14:39:58 +01:00 |
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Nick Gasson
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d08f5af9c6
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Add concurrent assignments
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2008-06-09 14:21:55 +01:00 |
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Nick Gasson
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120b5dc80e
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Add constant integers
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2008-06-09 12:46:55 +01:00 |
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Nick Gasson
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d762253f74
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Wait statements
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2008-06-09 12:40:59 +01:00 |
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Nick Gasson
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1d28b935e8
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Split vhdl_element.cc into multiple files
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2008-06-08 13:27:48 +01:00 |