If there are errors when parsing a file, it is not safe to elaborate any
modules that have been found in that file.
(cherry picked from commit 0cb1ebddf1)
Also reword the warning for SystemVerilog, where `timescale is not
the only (or indeed preferred) way of specifying timescales.
(cherry picked from commit 9382d22063)
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
(cherry picked from commit 7bed181f68)
If all three rise/fall/decay delay values are constant, we can use
the vvp .delay statement variant that takes three literal numbers.
If not, we have to use the variant that takes three net inputs. If
some of the delay values are constant, we need to create constant
drivers for those delay inputs.
(cherry picked from commit 20104c92c8)
A compressed assignment statement should give exactly the same
result as the equivalent uncompressed statement. This means
that the type (signed/unsigned) of the LHS affects the type of
the RHS expression (unlike in normal assignments). We need to
take care that bit/part selects and concatenations are correctly
identified as unsigned values, even in the cases where they
reduce to a single whole signal.
(cherry picked from commit 0199ad129d)
In generate blocks such as for loops, there may be many generated
scopes that have the same generated name. But in these cases, there
is an index number in the hname that can be used. So do so.
(cherry picked from commit 81f54ec0cb)
The reported problem was caused by a null statement in a case statement,
which caused the check for an infinite loop to fail. Further testing
exposed more problems with null statements in loop statements - these
caused crashes earlier in elaboration.
Implicit ports may be unnamed, either because the port expression
is not a simple/escaped identifier, or because there is no port
expression. To handle these cases, error messages should report
the port position as well as the port name.
The compiler was correctly detecting and reporting errors in loop
expressions and statements, but then crashing when it tried to build
the sensitivity list. Fix this by not adding a loop statement to the
netlist unless all its components have been successfully elaborated.
When unsized literals are used in case item expressions, it is likely
that the calculated expression width will be larger than necessary to
unambiguously select the correct case item (particularly when using
"strict" expression elaboration). This patch adds an optimisation
step that prunes the expressions to the minimum necessary width.
This goes all the way down to the vvp level, where we create support
for arrays of objects, generate the new code in the -tvvp code
generator, and elaborate the arrays in the first place.
The parser always passes a single NULL argument for system tasks. For a
method call which will add a signal to call the method on we need to
ignore this NULL argument.
This required keeping for-loops as actual things through the
netlist form so that the synthesizer can get at and understand
the parts of the for-loop. This may improve vvp code generation
in the future, but for now continue to present to the vvp code
generation the block-while form.
Cary R
Stephen Williams
Martin Whitaker
Martin Whitaker
Larry Doolittle
Maciej Suminski