Fix assertion failure when top level module has array ports.

Reported by Kustaa Nyholm on iverilog-devel, 2017-10-17. (cherry picked from commit a8318db21c)
2019-08-03 18:52:49 +01:00 · 2019-08-03 18:52:49 +01:00 · b7b22660e5
parent a6eb59192e
commit b7b22660e5
1 changed files with 1 additions and 2 deletions
--- a/elaborate.cc
+++ b/elaborate.cc
@ -6411,8 +6411,7 @@ Design* elaborate(list<perm_string>roots)
 			if (netnet != 0) {
 			  // Elaboration may actually fail with
 			  // erroneous input source
-			  ivl_assert(*mport[pin], netnet->pin_count()==1);
-                          prt_vector_width += netnet->vector_width();
+                          prt_vector_width += netnet->vector_width() * netnet->pin_count();
                          ptype = PortType::merged(netnet->port_type(), ptype);
 			}
 		  }