Commit Graph

77 Commits

Author SHA1 Message Date
steve a8b86ea3bb More explicit datatype setup. 2006-05-01 20:47:58 +00:00
steve dc2898cc73 fix net type of multiply output. 2006-05-01 05:40:21 +00:00
steve 0c9fb766b6 Get the data type of part select results right. 2006-04-30 05:17:48 +00:00
steve a4116efd57 Fix the return type of a synthesized divide. 2006-01-03 05:15:33 +00:00
steve 7235706923 Make sure div, mod and mult nodes have line number info. 2005-09-15 23:04:09 +00:00
steve b69f59f2ec Handle memory references is continuous assignments. 2005-08-31 05:07:31 +00:00
steve 73f3589ea6 use NetPartSelect to shrink part from high bits. 2005-06-13 23:22:14 +00:00
steve 9278dad244 Make synthesized padding vector-aware. 2005-06-13 22:26:03 +00:00
steve 3bd09d1470 synthesis of Logic and shifts using vector gates. 2005-05-15 04:47:00 +00:00
steve d548c9a5f8 Handle synthesis of concatenation expressions. 2005-05-06 00:25:13 +00:00
steve af7e196518 synthesis of add and unary get vector widths right. 2005-04-25 01:30:31 +00:00
steve 365cfedd55 Update DFF support to new data flow. 2005-04-24 23:44:01 +00:00
steve ab1ca54df2 Update support for LPM_MOD. 2005-03-12 06:43:35 +00:00
steve 257e1f9516 Support shifts and divide. 2005-02-19 02:43:38 +00:00
steve d74177634c Restructure NetMux devices to pass vectors.
Generate NetMux devices from ternary expressions,
 Reduce NetMux devices to bufif when appropriate.
2005-02-12 06:25:40 +00:00
steve 99ace10774 Simplified NetMult and IVL_LPM_MULT. 2005-01-28 05:39:33 +00:00
steve bf6a5d0f50 Implement LPM_COMPARE nodes as two-input vector functors. 2005-01-16 04:20:32 +00:00
steve 65e9b6be12 Rework of internals to carry vectors through nexus instead
of single bits. Make the ivl, tgt-vvp and vvp initial changes
 down this path.
2004-12-11 02:31:25 +00:00
steve 3dbc07f34d Implement signed divide and signed right shift in nets. 2004-06-30 02:16:26 +00:00
steve 2d63705093 Connect rsif of multiply to DataB. 2004-06-16 16:21:34 +00:00
steve e8e0cd7cab Support / and % in synthesized contexts. 2004-06-12 15:00:02 +00:00
steve ba309e60bb Fix synthesis method for logical and/or 2004-06-01 01:04:57 +00:00
steve 177b6ffb6a Addtrbute keys are perm_strings. 2004-02-20 18:53:33 +00:00
steve 27af95d402 Use perm_strings for named langiage items. 2004-02-18 17:11:54 +00:00
steve 2f8a40b159 Fix evaluation of compare to constant expression. 2004-02-15 04:23:48 +00:00
steve 8eccb7b9a1 Remove redundant scope tokens. 2003-11-10 19:39:20 +00:00
steve 4eae8426a9 More flexible width handling for synthesized add. 2003-10-27 06:04:21 +00:00
steve 1cb589fee0 Assure ternary arguments are wide enough. 2003-09-26 02:44:27 +00:00
steve b0230cf4d4 Support synthesis of constant downshifts. 2003-09-03 23:31:36 +00:00
steve 7c1401a2ba Spelling patch. 2003-08-28 04:11:17 +00:00
steve a95463ff81 Add support for IVL_LPM_MULT device. 2003-08-09 03:23:03 +00:00
steve bfe31e22bf Start handling pad of expressions in code generators. 2003-07-26 03:34:42 +00:00
steve 21ff80075a Various warnings fixed. 2003-06-24 01:38:02 +00:00
steve 58f5955687 Less picky about expression widths while synthesizing ternary. 2003-04-19 04:52:56 +00:00
steve 58f2fe73c8 Detect constant shift distances in synthesis. 2003-04-08 05:07:15 +00:00
steve 2c129dfbfa Synthesize shift expressions. 2003-04-08 04:33:55 +00:00
steve badad63ab4 All NetObj objects have lex_string base names. 2003-03-06 00:28:41 +00:00
steve a275133ff9 LPM objects store only their base names. 2003-02-26 01:29:24 +00:00
steve e941e7e805 Spelling fixes. 2003-01-30 16:23:07 +00:00
steve 46253ed873 Rework expression parsing and elaboration to
accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
steve 0ccb9139c9 Magnitude compare to 0. 2002-11-17 23:37:55 +00:00
steve 52bf4e613f conditional ident string using autoconfig. 2002-08-12 01:34:58 +00:00
steve 33ee1da817 Smart synthesis of binary AND expressions. 2002-07-07 22:31:39 +00:00
steve 301040a67a Avoid emitting to vvp local net symbols. 2002-07-05 21:26:17 +00:00
steve bfad382fd1 Carry Verilog 2001 attributes with processes,
all the way through to the ivl_target API.

 Divide signal reference counts between rval
 and lval references.
2002-05-26 01:39:02 +00:00
steve e6c0629626 Add language support for Verilog-2001 attribute
syntax. Hook this support into existing $attribute
 handling, and add number and void value types.

 Add to the ivl_target API new functions for access
 of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
steve 1a22f37d92 Synthesize reduction logic. 2001-12-30 17:06:52 +00:00
steve dddbeb957a Comments about MUX synthesis. 2001-12-18 05:34:02 +00:00
steve e85347bf8b Handle part selects in l-values of DFF devices. 2001-11-29 01:58:18 +00:00
steve 874bab10e4 NetObj constructor finally requires a scope. 2001-10-28 01:14:53 +00:00