iverilog

Author	SHA1	Message	Date
Stephen Williams	f138b0d631	Be more precide about mappings to Verilog types. Make std_logic map to Verilog logic, and integers and bits map to Verilog bool. These are more precise and accurate.	2011-02-13 16:48:52 -08:00
Stephen Williams	b08ab3448e	Emit net declarations. Rather then leave net types to implicit declarations, write declarations explicitly. This will become necessary when more interesting types are supported.	2011-02-13 16:48:52 -08:00
Stephen Williams	5914617727	Clean up entity interface.	2011-02-13 16:48:52 -08:00
Stephen Williams	798ead9345	Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.	2011-02-13 16:48:52 -08:00