b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
3bd480a375
Allow ouput to be read if connected to child output
...
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
4e73b1b133
Fix bug when resolving nexus to VHDL signal
2008-06-30 17:47:45 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
bf95d77562
Finish replacing vhdl_process with vhdl_procedural
2008-06-24 20:01:06 +01:00
db992e808f
Start using vhdl_procedural instead of vhdl_process
2008-06-24 19:54:22 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
404c22ac86
Improved implementation of $display
2008-06-20 11:51:13 +01:00
e0f41198d6
Blocking assignment working correctly
2008-06-18 13:49:03 +01:00
fb31a88c51
Blocking assignment nearly working
2008-06-18 13:30:19 +01:00
254ccb9ccb
First passing at blocking assignment
2008-06-18 13:06:27 +01:00
d2bebee9d9
Refactor before adding blocking assignment
2008-06-18 12:51:11 +01:00
af8c08e6a7
Allow optional VHPI $finish implementation
2008-06-17 20:16:16 +01:00
561953e494
Minial LPM to support continuous assignments
2008-06-16 19:41:01 +01:00
b8c1f9ab67
A system for linking ivl_signal_t to entities
2008-06-12 20:26:23 +01:00
a7cfdc3a87
Add VHDL if statement to AST types
2008-06-11 14:11:37 +01:00
1d28b935e8
Split vhdl_element.cc into multiple files
2008-06-08 13:27:48 +01:00
9f035108e1
Stub code for translating expressions
2008-06-04 14:59:04 +01:00
4bf2e1669d
Store packages required with entity rather than globally
...
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
fe80da362c
Collect required packages as compilation progresses
2008-06-03 19:14:47 +01:00
4211e651d0
Stub file for processing statements
2008-06-03 18:26:36 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
8189c4ee43
Generate VHDL entities and architectures for all module scopes
2008-05-31 15:28:25 +01:00
e38494a10c
Pretty-print VHDL output
2008-05-29 16:24:16 +01:00
bfa2bfc8ae
Makefile and autoconf changes to build VHDL code generator
2008-05-28 17:17:39 +01:00
Nick Gasson