fef81958bc
Do not generate code for signals,
...
instead use the NetESignal node to
generate gate-like signal devices.
1999-02-08 03:55:55 +00:00
30a3953c85
Turn the NetESignal into a NetNode so
...
that it can connect to the netlist.
Implement the case statement.
Convince t-vvm to output code for
the case statement.
1999-02-08 02:49:56 +00:00
d1e2b036fc
Add startup after initialization.
1999-01-01 01:46:01 +00:00
63a8b4abe2
Function to calculate wire initial value.
1998-12-20 02:05:41 +00:00
4e2c0036aa
VVM support for small sequential UDP objects.
1998-12-17 23:54:58 +00:00
af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
7859de1e4e
Add support it vvm target for level-sensitive
...
triggers (i.e. the Verilog wait).
Fix display of $time is format strings.
1998-11-10 00:48:31 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
47a444fb92
Calculate expression widths at elaboration time.
1998-11-07 19:17:10 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve