090ae5fa56
Catch case where signal with same name in task and module
...
This fixes task3.14C
2008-08-08 19:47:20 +01:00
13cb81f4bb
Add task signals to containing architecture
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This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
ef66ca6498
Do a part select of the array selection result not the base array.
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When doing the part select of an array selection you need to use
the result from the array selection to do the part select not the
base array signal.
2008-08-07 20:45:58 -07:00
d43452f88d
Check all generate expressions for failure.
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This patch adds code to check that the various generate expressions
evaluate correctly.
2008-08-07 20:41:24 -07:00
e719dc250a
%load/av now matches %load/v for truncating/extension.
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This patch adds code to make %load/av extend or truncate
a value like %load/v.
2008-08-07 20:34:20 -07:00
bb0efda526
Make make_safe_name case insensitive
2008-08-07 17:58:42 +01:00
e4d0a92d7c
Division and modulus operators
2008-08-07 14:18:26 +01:00
28d782e13c
Remove redundant verilog_support.vhd file
2008-08-07 13:10:53 +01:00
6f5f700cb9
Very minimal implementation of tasks
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This expands the task in-line inside the process to avoid
problems with global variables (VHDL processes cannot
reference globals)
2008-08-07 10:54:39 +01:00
a17924f819
Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
2008-08-07 09:19:13 +01:00
893aae2ca4
Add BUFZ to input ports when necessary.
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When driving an input port to a module, watch out for the case where
the net is also driven within the instance. If this is the case, take
pains to make sure what goes on in the instance doesn't leak out
through the input port. Add a BUFZ (continuous assignment) to isolate
the context from internal driving.
2008-08-06 21:04:52 -07:00
4cbec1c817
Add XNOR binary operand
2008-08-06 11:18:01 +01:00
d84771428a
need to decrement string len if we have a '-' sign
2008-08-05 15:26:29 -07:00
484d3ea36b
this patch adds support for conversion of negative vpiDecStrVal in vpip_dec_str_to_vec4()
2008-08-05 15:26:22 -07:00
c71e930ffa
$fscanf("%s"): accept '-' and '_' chars.
2008-08-05 15:26:16 -07:00
15584a4f81
fix $fscan("%d") for values > 32 bit
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The old code returns a vpiIntVal for $fscanf("%d") format strings. This
limits the maximum input range arbitrarily to 32 bit.
This patch implements %d parsing similiar to %b and %x.
'?' and 'X' chars are not accepted for %d format.
2008-08-05 15:26:09 -07:00
f86f454956
Apply the last patch to if/case statements too
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This further cleans up the output by removing more
useless `wait for 0ns' statements.
2008-08-05 11:09:51 +01:00
e01e038cf9
Avoid generating useless `wait for 0ns' statements
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If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
2008-08-05 11:02:36 +01:00
c849dfeec4
Add XNOR logic device
2008-08-05 10:45:01 +01:00
8d7b03576c
Correctly implement unary XNOR
...
Forgot to negate the output.
2008-08-05 10:38:43 +01:00
b292a5fc05
Create a branch object to be the argument to the access function.
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The NetBranch object is connected, but not like an object, so the
NetPins object base class is factored out from NetObj to handle the
connectivity, and the NetBranch class uses the NetPins to connect a
branch.
Also, account for the fact that nets with a discipline are by default
real-valued.
2008-08-04 20:54:05 -07:00
72019959a8
Translate some ternary expressions to if statements
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This re-implements some earlier functionality where
ternary expressions on an assignment RHS are translated
to an if statement.
2008-08-03 15:47:32 +01:00
9565ea1034
Add some whitespace above component instantiations
2008-08-03 14:50:13 +01:00
49a2693357
Add file / line number information to functions
2008-08-03 14:46:57 +01:00
10a5ca199d
Add file / line number comments to instantiations
2008-08-03 14:38:08 +01:00
c2f622327f
Use ivl_scope_def_* for definition file/line numbers
2008-08-03 14:34:41 +01:00
0e2628a3fb
Minimal implementation of IVL_LPM_MUX
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This handles the (common) case of the select being only
1 bit wide. Implemented as a concurrent assignment with
a `when' clause.
2008-08-03 12:46:50 +01:00
45dfa28dba
Remember signal pin a nexus was attached to
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Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
c8cbac58f5
Add forward declarations for functions
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This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
c1b5424ca6
Implement assignment with multiple lvals
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Multiple lvals are implemented by first assigning the complete
RHS to a temporary, and then assigning each lval in turn as
bit-selects of the temporary
2008-08-02 18:40:24 +01:00
c706c94e38
Generate a vhdl_var_ref for every assignment lval
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This completes the refactoring of make_assignment
necessary to implement multiple lvals.
2008-08-02 18:20:18 +01:00
fad8abee34
Start refactoring make_assignment for multiple lvals
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This patch lifts the RHS generating code out of the
lval-specific code and sticks a loop around the lvals.
2008-08-02 16:38:44 +01:00
9448c5939c
Always user Ternary_* support functions for ternary assignments
...
Previously the code generator expanded ternary assignments to
and `if' statement. This patch replaces that with a single assignment
and a call to a Ternary_* support function. This will make it
much easier to support multiple lvals later.
2008-08-02 15:46:36 +01:00
752a90dc2f
Insert blank line before VHDL process in output
2008-08-02 10:45:38 +01:00
a60216ec15
Use ivl_process_* functions for file/line number information
2008-08-02 10:44:03 +01:00
5d0df8d880
Change format of line file/line numbers
2008-08-02 10:42:00 +01:00
1cd13ecdbd
Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
2008-08-02 10:37:22 +01:00
c14987aa18
Merge branch 'master' into verilog-ams
2008-08-01 21:15:11 -07:00
aeec93a322
$time, $stime and $simtime return an integer rounded value for %f
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The $time, $stime, $simtime (integer time) system functions should
return a rounded integer value in a real context.
2008-08-01 20:37:41 -07:00
61930c3b6e
Add file and line information to processes.
...
This patch adds file and line information to processes
(initial and always).
2008-08-01 20:13:29 -07:00
296f1bacc1
vvp_vector4_t words are unsigned long.
...
The double to vvp_vector4_t constructor was not using the correct
declaration for the bit words. This worked as long as unsigned and
unsigned long were the same size (usually).
2008-08-01 20:10:52 -07:00
bb80b432e6
Add comments file/line number comments
...
Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
be551a6b68
Add a stub vvp_net_t::delete method
...
Some compilers reference the delete method for the vvp_net_t object
even though it is never used. So provide a stub with an assert.
2008-08-01 09:48:59 -07:00
e0834f7f38
Add NAND and NOR logic devices
2008-08-01 17:46:04 +01:00
a26d91557b
Add binary NAND and NOR operators
2008-08-01 17:42:26 +01:00
3f73c9bb54
Make sure argument to unary - is signed
2008-08-01 16:35:47 +01:00
09f3eb4a36
Don't bother calling reduction function if argument is std_logic
2008-08-01 16:27:55 +01:00
33885ed891
Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
2008-08-01 08:25:38 +01:00
d21277f1b9
Tidy up whitespace in output
2008-07-31 21:17:49 +01:00
7b0f675785
Add check for sequential UDPs
2008-07-31 21:08:59 +01:00
Nick Gasson
Cary R
Stephen Williams
Holger Wächtler