Commit Graph

204 Commits

Author SHA1 Message Date
steve 4493e968da Finally remove the NetNEvent and NetPEvent classes,
Get synthesis working with the NetEvWait class,
 and get started supporting multiple events in a
 wait in vvm.
2000-04-12 20:02:52 +00:00
steve b1fd927acb Named events really should be expressed with PEIdent
objects in the pform,

 Handle named events within the mix of net events
 and edges. As a unified lot they get caught together.
 wait statements are broken into more complex statements
 that include a conditional.

 Do not generate NetPEvent or NetNEvent objects in
 elaboration. NetEvent, NetEvWait and NetEvProbe
 take over those functions in the netlist.
2000-04-12 04:23:57 +00:00
steve 2dd010dc04 Named events as far as the pform. 2000-04-01 19:31:57 +00:00
steve 6eef54595f Support localparam. 2000-03-12 17:09:40 +00:00
steve e7efc2709a Redesign the implementation of scopes and parameters.
I now generate the scopes and notice the parameters
 in a separate pass over the pform. Once the scopes
 are generated, I can process overrides and evalutate
 paremeters before elaboration begins.
2000-03-08 04:36:53 +00:00
steve b734ecf02f Macintosh compilers do not support ident. 2000-02-23 02:56:53 +00:00
steve 5b52c384d6 Catch module instantiation arrays. 2000-02-18 05:15:02 +00:00
steve 9125a4c451 Careful with wires connected to multiple ports. 2000-01-09 20:37:57 +00:00
steve 2de887c2ff Support named parameter override lists. 2000-01-09 05:50:48 +00:00
steve 70a1236626 Structural case equals device. 1999-10-10 01:59:54 +00:00
steve c63a3acf93 Elaborate ~^ and ~| operators. 1999-09-30 02:43:01 +00:00
steve 6e486e9bcf Cope with errors during ternary operator elaboration. 1999-09-30 00:48:49 +00:00
steve 8e21f0f363 Handle some mor missing names. 1999-09-29 21:15:58 +00:00
steve 2271fc9894 Handle empty named ports in the dump. 1999-09-29 20:23:53 +00:00
steve a64a33e65a Full case support 1999-09-29 18:36:02 +00:00
steve 424e6a750c Handle unconnected module ports. 1999-09-17 02:06:25 +00:00
steve 9d82d19d07 Empty conditionals (pmonta@imedia.com) 1999-09-08 02:24:39 +00:00
steve 8f68a07476 Add support for delayed non-blocking assignments. 1999-09-04 19:11:45 +00:00
steve 23acca48ff elaborate some aspects of functions. 1999-08-25 22:22:41 +00:00
steve 9eae940ebd Parameter overrides support from Peter Monta
AND and XOR support wide expressions.
1999-08-23 16:48:39 +00:00
steve 4c219530c1 Proper port type names. 1999-08-03 04:49:13 +00:00
steve 5f10342f52 Parse into pform arbitrarily complex module
port declarations.
1999-08-03 04:14:49 +00:00
steve 71d35f32b2 Parse and elaborate rise/fall/decay times
for gates, and handle the rules for partial
 lists of times.
1999-08-01 16:34:50 +00:00
steve e0a988bf7e Add functions up to elaboration (Ed Carter) 1999-07-31 19:14:47 +00:00
steve d9553ecba1 Handle dumping tasks with no ports. 1999-07-30 00:43:17 +00:00
steve 93a77a2efd Elaborate task input ports. 1999-07-24 02:11:19 +00:00
steve a5921ceae8 netlist support for ternary operator. 1999-07-17 19:50:59 +00:00
steve 6852a62e5a procedural blocking assignment delays. 1999-07-12 00:59:36 +00:00
steve 3ff6912bdd Elaborate user defined tasks. 1999-07-03 02:12:51 +00:00
steve 11b2b1740a Handle expression widths for EEE and NEE operators,
add named blocks and scope handling,
 add registers declared in named blocks.
1999-06-24 04:24:18 +00:00
steve 853ad247a1 Elaborate and supprort to vvm the forever
and repeat statements.
1999-06-19 21:06:16 +00:00
steve 37b60a4c52 Clean up interface of the PWire class,
Properly match wire ranges.
1999-06-17 05:34:42 +00:00
steve fabb146342 Support case expression lists. 1999-06-15 05:38:39 +00:00
steve d0afc9adee Get rid of the STL vector template. 1999-06-15 03:44:53 +00:00
steve 740c63291a l-value part select for procedural assignments. 1999-06-13 23:51:16 +00:00
steve 7c2cf8b2fa Add support for the Ternary operator,
Add support for repeat concatenation,
 Correct some seg faults cause by elaboration
 errors,
 Parse the casex anc casez statements.
1999-06-10 04:03:52 +00:00
steve 7605a7b1f0 Add parse and elaboration of non-blocking assignments,
Replace list<PCase::Item*> with an svector version,
 Add integer support.
1999-06-06 20:45:38 +00:00
steve 35893919e0 module parameter bind by name. 1999-05-29 02:36:17 +00:00
steve 5de9b7c9f1 Parse and elaborate the concatenate operator
in structural contexts, Replace vector<PExpr*>
 and list<PExpr*> with svector<PExpr*>, evaluate
 constant expressions with parameters, handle
 memories as lvalues.

 Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
steve b44ef063a8 Fix handling of null delay statements. 1999-05-05 03:04:46 +00:00
steve 41f9a84a4b Handle much more complex event expressions. 1999-05-01 02:57:52 +00:00
steve ce49708442 Parse OR of event expressions. 1999-04-29 02:16:26 +00:00
steve 5895d3c98d Add memories to the parse and elaboration phases. 1999-04-19 01:59:36 +00:00
steve e2a37a8ccd Add support for module parameters. 1999-02-21 17:01:57 +00:00
steve e5f5f41515 Elaborate gate ranges. 1999-02-15 02:06:15 +00:00
steve 8bdd381cdf Parse and elaborate the Verilog CASE statement. 1999-02-03 04:20:11 +00:00
steve a7ad8985ac Carry some line info to the netlist,
Dump line numbers for processes.
 Elaborate prints errors about port vector
 width mismatch
 Emit better handles null statements.
1999-02-01 00:26:48 +00:00
steve e097c999d5 Elaborate UDP devices,
Support UDP type attributes, and
 pass those attributes to nodes that
 are instantiated by elaboration,
 Put modules into a map instead of
 a simple list.
1998-12-01 00:42:13 +00:00
steve 91aad30e1f Parse UDP primitives all the way to pform. 1998-11-25 02:35:53 +00:00
steve af8d6fbf01 NetAssign handles lvalues as pin links
instead of a signal pointer,
 Wire attributes added,
 Ability to parse UDP descriptions added,
 XNF generates EXT records for signals with
 the PAD attribute.
1998-11-23 00:20:22 +00:00
steve 6b2fa19429 Handle while loops. 1998-11-11 03:13:04 +00:00
steve ebad845fc3 Add procedural while loops,
Parse procedural for loops,
 Add procedural wait statements,
 Add constant nodes,
 Add XNOR logic gate,
 Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
steve b118634189 Handle procedural conditional, and some
of the conditional expressions.

 Elaborate signals and identifiers differently,
 allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00