Structural case equals device.
This commit is contained in:
steve
parent
7201865554
commit
70a1236626
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: design_dump.cc,v 1.49 1999/10/08 02:00:35 steve Exp $"
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#ident "$Id: design_dump.cc,v 1.50 1999/10/10 01:59:54 steve Exp $"
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#endif
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/*
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@ -153,6 +153,12 @@ void NetBUFZ::dump_node(ostream&o, unsigned ind) const
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dump_node_pins(o, ind+4);
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}
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void NetCaseCmp::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "case compare === : " << name() << endl;
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dump_node_pins(o, ind+4);
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}
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void NetConst::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "constant " << value_ << ": " << name() << endl;
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@ -789,6 +795,9 @@ void Design::dump(ostream&o) const
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/*
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* $Log: design_dump.cc,v $
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* Revision 1.50 1999/10/10 01:59:54 steve
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* Structural case equals device.
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*
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* Revision 1.49 1999/10/08 02:00:35 steve
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* Fix dump of sase statements.
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*
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75
elaborate.cc
75
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.115 1999/10/09 21:30:16 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.116 1999/10/10 01:59:54 steve Exp $"
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#endif
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/*
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@ -720,6 +720,76 @@ NetNet* PEBinary::elaborate_net(Design*des, const string&path,
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des->add_signal(osig);
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break;
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case 'a': // && (logical AND)
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gate = new NetLogic(des->local_symbol(path), 3, NetLogic::AND);
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// The first OR gate returns 1 if the left value is true...
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if (lsig->pin_count() > 1) {
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gate_t = new NetLogic(des->local_symbol(path),
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1+lsig->pin_count(), NetLogic::OR);
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for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1)
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connect(gate_t->pin(idx+1), lsig->pin(idx));
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connect(gate->pin(1), gate_t->pin(0));
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des->add_node(gate_t);
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} else {
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connect(gate->pin(1), lsig->pin(0));
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}
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// The second OR gate returns 1 if the right value is true...
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if (rsig->pin_count() > 1) {
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gate_t = new NetLogic(des->local_symbol(path),
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1+rsig->pin_count(), NetLogic::OR);
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for (unsigned idx = 0 ; idx < rsig->pin_count() ; idx += 1)
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connect(gate_t->pin(idx+1), rsig->pin(idx));
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connect(gate->pin(2), gate_t->pin(0));
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des->add_node(gate_t);
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} else {
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connect(gate->pin(2), rsig->pin(0));
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}
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// The output is the AND of the two logic values.
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osig = new NetNet(des->local_symbol(path), NetNet::WIRE);
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osig->local_flag(true);
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connect(gate->pin(0), osig->pin(0));
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des->add_signal(osig);
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gate->rise_time(rise);
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gate->fall_time(fall);
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gate->decay_time(decay);
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des->add_node(gate);
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break;
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case 'E': // === (Case equals)
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// The comparison generates gates to bitwise compare
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// each pair, and AND all the comparison results.
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assert(lsig->pin_count() == rsig->pin_count());
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osig = new NetNet(des->local_symbol(path), NetNet::WIRE);
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osig->local_flag(true);
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gate = new NetLogic(des->local_symbol(path),
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1+lsig->pin_count(),
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NetLogic::AND);
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connect(gate->pin(0), osig->pin(0));
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for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
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gate_t = new NetCaseCmp(des->local_symbol(path));
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connect(gate_t->pin(1), lsig->pin(idx));
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connect(gate_t->pin(2), rsig->pin(idx));
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connect(gate_t->pin(0), gate->pin(idx+1));
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des->add_node(gate_t);
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// Attach a label to this intermediate wire
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NetNet*tmp = new NetNet(des->local_symbol(path),
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NetNet::WIRE);
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tmp->local_flag(true);
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connect(gate_t->pin(0), tmp->pin(0));
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des->add_signal(tmp);
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}
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des->add_signal(osig);
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gate->rise_time(rise);
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gate->fall_time(fall);
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gate->decay_time(decay);
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des->add_node(gate);
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break;
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case 'e': // ==
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assert(lsig->pin_count() == rsig->pin_count());
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osig = new NetNet(des->local_symbol(path), NetNet::WIRE);
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@ -2614,6 +2684,9 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.116 1999/10/10 01:59:54 steve
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* Structural case equals device.
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*
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* Revision 1.115 1999/10/09 21:30:16 steve
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* Support parameters in continuous assignments.
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*
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10
emit.cc
10
emit.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: emit.cc,v 1.23 1999/09/22 16:57:23 steve Exp $"
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#ident "$Id: emit.cc,v 1.24 1999/10/10 01:59:54 steve Exp $"
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#endif
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/*
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@ -60,6 +60,11 @@ void NetAssignNB::emit_node(ostream&o, struct target_t*tgt) const
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tgt->net_assign_nb(o, this);
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}
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void NetCaseCmp::emit_node(ostream&o, struct target_t*tgt) const
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{
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tgt->net_case_cmp(o, this);
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}
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void NetConst::emit_node(ostream&o, struct target_t*tgt) const
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{
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tgt->net_const(o, this);
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@ -352,6 +357,9 @@ bool emit(ostream&o, const Design*des, const char*type)
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/*
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* $Log: emit.cc,v $
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* Revision 1.24 1999/10/10 01:59:54 steve
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* Structural case equals device.
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*
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* Revision 1.23 1999/09/22 16:57:23 steve
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* Catch parallel blocks in vvm emit.
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*
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27
netlist.cc
27
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.cc,v 1.75 1999/10/07 05:25:34 steve Exp $"
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#ident "$Id: netlist.cc,v 1.76 1999/10/10 01:59:55 steve Exp $"
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#endif
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# include <cassert>
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@ -599,6 +599,18 @@ void NetCase::set_case(unsigned idx, NetExpr*e, NetProc*p)
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items_[idx].guard->set_width(expr_->expr_width());
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}
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NetCaseCmp::NetCaseCmp(const string&n)
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: NetNode(n, 3)
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{
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pin(0).set_dir(Link::OUTPUT);
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pin(1).set_dir(Link::INPUT);
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pin(2).set_dir(Link::INPUT);
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}
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NetCaseCmp::~NetCaseCmp()
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{
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}
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NetCondit::NetCondit(NetExpr*ex, NetProc*i, NetProc*e)
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: expr_(ex), if_(i), else_(e)
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{
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@ -631,6 +643,16 @@ NetProc* NetCondit::else_clause()
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return else_;
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}
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NetConst::NetConst(const string&n, verinum::V v)
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: NetNode(n, 1), value_(v)
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{
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pin(0).set_dir(Link::OUTPUT);
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}
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NetConst::~NetConst()
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{
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}
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NetFuncDef::NetFuncDef(const string&n, const svector<NetNet*>&po)
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: name_(n), statement_(0), ports_(po)
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{
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@ -1732,6 +1754,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
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/*
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* $Log: netlist.cc,v $
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* Revision 1.76 1999/10/10 01:59:55 steve
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* Structural case equals device.
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*
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* Revision 1.75 1999/10/07 05:25:34 steve
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* Add non-const bit select in l-value of assignment.
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*
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31
netlist.h
31
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.78 1999/10/07 05:25:34 steve Exp $"
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#ident "$Id: netlist.h,v 1.79 1999/10/10 01:59:55 steve Exp $"
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#endif
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/*
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@ -431,11 +431,33 @@ class NetBUFZ : public NetNode {
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virtual void emit_node(ostream&, struct target_t*) const;
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};
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/*
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* This node is used to represent case equality in combinational
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* logic. Although this is not normally synthesizeable, it makes sense
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* to support an abstract gate that can compare x and z.
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*
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* This pins are assigned as:
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*
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* 0 -- Output (always returns 0 or 1)
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* 1 -- Input
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* 2 -- Input
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*/
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class NetCaseCmp : public NetNode {
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public:
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explicit NetCaseCmp(const string&n);
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~NetCaseCmp();
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virtual void dump_node(ostream&, unsigned ind) const;
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virtual void emit_node(ostream&, struct target_t*) const;
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};
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class NetConst : public NetNode {
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public:
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explicit NetConst(const string&n, verinum::V v)
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: NetNode(n, 1), value_(v) { pin(0).set_dir(Link::OUTPUT); }
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explicit NetConst(const string&n, verinum::V v);
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~NetConst();
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verinum::V value() const { return value_; }
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@ -1711,6 +1733,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.79 1999/10/10 01:59:55 steve
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* Structural case equals device.
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*
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* Revision 1.78 1999/10/07 05:25:34 steve
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* Add non-const bit select in l-value of assignment.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: pform_dump.cc,v 1.44 1999/09/30 02:43:02 steve Exp $"
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#ident "$Id: pform_dump.cc,v 1.45 1999/10/10 01:59:55 steve Exp $"
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#endif
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/*
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@ -132,6 +132,9 @@ void PEBinary::dump(ostream&out) const
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{
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out << "(" << *left_ << ")";
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switch (op_) {
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case 'a':
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out << "&&";
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break;
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case 'e':
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out << "==";
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break;
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@ -672,6 +675,9 @@ void PUdp::dump(ostream&out) const
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/*
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* $Log: pform_dump.cc,v $
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* Revision 1.45 1999/10/10 01:59:55 steve
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* Structural case equals device.
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*
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* Revision 1.44 1999/09/30 02:43:02 steve
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* Elaborate ~^ and ~| operators.
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*
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22
t-vvm.cc
22
t-vvm.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-vvm.cc,v 1.61 1999/10/08 02:00:48 steve Exp $"
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#ident "$Id: t-vvm.cc,v 1.62 1999/10/10 01:59:55 steve Exp $"
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#endif
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# include <iostream>
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@ -55,6 +55,7 @@ class target_vvm : public target_t {
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virtual void bufz(ostream&os, const NetBUFZ*);
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virtual void udp(ostream&os, const NetUDP*);
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virtual void net_assign_nb(ostream&os, const NetAssignNB*);
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virtual void net_case_cmp(ostream&os, const NetCaseCmp*);
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virtual void net_const(ostream&os, const NetConst*);
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virtual void net_esignal(ostream&os, const NetESignal*);
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virtual void net_event(ostream&os, const NetNEvent*);
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@ -1008,6 +1009,22 @@ void target_vvm::net_assign_nb(ostream&os, const NetAssignNB*net)
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delayed << "}" << endl;
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}
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void target_vvm::net_case_cmp(ostream&os, const NetCaseCmp*gate)
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{
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os << "static void " << mangle(gate->name()) <<
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"_output_fun(vvm_simulation*, vvm_bit_t);" << endl;
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assert(gate->pin_count() == 3);
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os << "static vvm_eeq" << "<" << gate->rise_time() << "> "
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<< mangle(gate->name()) << "(&" << mangle(gate->name()) <<
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"_output_fun);" << endl;
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emit_gate_outputfun_(gate);
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start_code << " " << mangle(gate->name()) <<
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".start(&sim);" << endl;
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}
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/*
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* The NetConst is a synthetic device created to represent constant
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* values. I represent them in the output as a vvm_bufz object that
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@ -1727,6 +1744,9 @@ extern const struct target tgt_vvm = {
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};
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/*
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* $Log: t-vvm.cc,v $
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* Revision 1.62 1999/10/10 01:59:55 steve
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* Structural case equals device.
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*
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* Revision 1.61 1999/10/08 02:00:48 steve
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* vvm supports unary | operator.
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*
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11
target.cc
11
target.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: target.cc,v 1.20 1999/09/22 16:57:24 steve Exp $"
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#ident "$Id: target.cc,v 1.21 1999/10/10 01:59:55 steve Exp $"
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#endif
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# include "target.h"
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@ -85,6 +85,12 @@ void target_t::net_assign_nb(ostream&os, const NetAssignNB*)
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"Unhandled non-blocking assignment node." << endl;
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}
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void target_t::net_case_cmp(ostream&os, const NetCaseCmp*)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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"Unhandled case compare node." << endl;
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}
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void target_t::net_const(ostream&os, const NetConst*)
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{
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cerr << "target (" << typeid(*this).name() << "): "
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@ -269,6 +275,9 @@ void expr_scan_t::expr_binary(const NetEBinary*ex)
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/*
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* $Log: target.cc,v $
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* Revision 1.21 1999/10/10 01:59:55 steve
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* Structural case equals device.
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*
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* Revision 1.20 1999/09/22 16:57:24 steve
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* Catch parallel blocks in vvm emit.
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*
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|
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6
target.h
6
target.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: target.h,v 1.19 1999/09/22 16:57:24 steve Exp $"
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#ident "$Id: target.h,v 1.20 1999/10/10 01:59:55 steve Exp $"
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#endif
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# include "netlist.h"
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@ -74,6 +74,7 @@ struct target_t {
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virtual void udp(ostream&os, const NetUDP*);
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virtual void net_assign(ostream&os, const NetAssign*);
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virtual void net_assign_nb(ostream&os, const NetAssignNB*);
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virtual void net_case_cmp(ostream&os, const NetCaseCmp*);
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virtual void net_const(ostream&os, const NetConst*);
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virtual void net_esignal(ostream&os, const NetESignal*);
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virtual void net_event(ostream&os, const NetNEvent*);
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@ -136,6 +137,9 @@ extern const struct target *target_table[];
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/*
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* $Log: target.h,v $
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* Revision 1.20 1999/10/10 01:59:55 steve
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* Structural case equals device.
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*
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* Revision 1.19 1999/09/22 16:57:24 steve
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* Catch parallel blocks in vvm emit.
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*
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|
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|
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@ -19,7 +19,7 @@
|
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
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#if !defined(WINNT)
|
||||
#ident "$Id: vvm_gates.h,v 1.13 1999/10/09 19:24:36 steve Exp $"
|
||||
#ident "$Id: vvm_gates.h,v 1.14 1999/10/10 01:59:55 steve Exp $"
|
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#endif
|
||||
|
||||
# include "vvm.h"
|
||||
|
|
@ -346,6 +346,47 @@ template <unsigned WIDTH, unsigned long DELAY> class vvm_xor {
|
|||
vvm_out_event::action_t output_;
|
||||
};
|
||||
|
||||
/*
|
||||
* This gate has only 3 pins, the output at pin 0 and two inputs. The
|
||||
* output is 1 or 0 if the two inputs are exactly equal or not.
|
||||
*/
|
||||
template <unsigned long DELAY> class vvm_eeq {
|
||||
|
||||
public:
|
||||
explicit vvm_eeq(vvm_out_event::action_t o)
|
||||
: output_(o) { }
|
||||
|
||||
void init(unsigned idx, vvm_bit_t val)
|
||||
{ input_[idx-1] = val; }
|
||||
|
||||
void start(vvm_simulation*sim)
|
||||
{ vvm_event*ev = new vvm_out_event(sim, compute_(), output_);
|
||||
if (DELAY > 0)
|
||||
sim->insert_event(DELAY, ev);
|
||||
else
|
||||
sim->active_event(ev);
|
||||
}
|
||||
|
||||
void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
|
||||
{ if (input_[idx-1] == val)
|
||||
return;
|
||||
input_[idx-1] = val;
|
||||
start(sim);
|
||||
}
|
||||
|
||||
private:
|
||||
|
||||
vvm_bit_t compute_() const
|
||||
{ vvm_bit_t outval = V0;
|
||||
if (input_[0] == input_[1])
|
||||
outval = V1;
|
||||
return outval;
|
||||
}
|
||||
|
||||
vvm_bit_t input_[2];
|
||||
vvm_out_event::action_t output_;
|
||||
};
|
||||
|
||||
/*
|
||||
* A Sequential UDP has a more complex truth table, and handles
|
||||
* edges. Pin 0 is an output, and all the remaining pins are
|
||||
|
|
@ -496,6 +537,9 @@ template <unsigned WIDTH> class vvm_pevent {
|
|||
|
||||
/*
|
||||
* $Log: vvm_gates.h,v $
|
||||
* Revision 1.14 1999/10/10 01:59:55 steve
|
||||
* Structural case equals device.
|
||||
*
|
||||
* Revision 1.13 1999/10/09 19:24:36 steve
|
||||
* NOR device.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue