Commit Graph

175 Commits

Author SHA1 Message Date
Maciej Suminski 25458b8cc2 vhdlpp: inout direction for ports. 2015-05-19 22:40:56 +02:00
Maciej Suminski 5101b3b64b vhdlpp: Boolean values handled without using keywords. 2015-04-24 13:39:41 +02:00
Maciej Suminski bed5ee4529 vhdlpp: Handle 'severity' statements without using keywords. 2015-04-24 13:39:41 +02:00
Maciej Suminski 7c0a191626 vhdlpp: Handle true/false values. 2015-04-23 11:58:40 +02:00
Maciej Suminski cfa43c7742 vhdlpp: Support for reports & asserts. 2015-04-23 11:58:40 +02:00
Maciej Suminski 0ca856d4e8 bugfix #942: VHDL function bodies in arch declaration not supported 2015-03-31 10:46:24 +02:00
Maciej Suminski d5ffb55bfd Corrected ambiguous copyright info. 2015-03-27 18:57:40 +01:00
Maciej Suminski afbda099fb vhdlpp: Workaround to handle constant arrays of vectors & records. 2015-03-06 17:32:25 +01:00
Maciej Suminski 763c6fe3c9 vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
Maciej Suminski 49b6ddf93c vhdlpp: Signal/variable assignments can have labels. 2015-02-17 10:15:57 +01:00
Maciej Suminski 12b4914b63 vhdlpp: ExpName resolves enum values. 2015-02-17 10:15:57 +01:00
Maciej Suminski 5b7b980ead vhdlpp: Support for multiple choices in case statements. 2015-02-05 12:00:25 +01:00
Maciej Suminski a1c2a8e605 vhdlpp: Generic syntax errors display messages. 2015-02-05 11:25:03 +01:00
Cary R e896f0c8e6 Remove some compile warnings in the vhdlpp code 2014-10-14 09:03:42 -07:00
Maciej Suminski 9ff9cbf4aa vhdlpp: Smarter determining the direction in for loops. 2014-10-10 18:39:14 +02:00
Maciej Suminski c7beef907d vhdlpp: Support for 'range and 'reverse_range attributes. 2014-10-08 11:18:06 +02:00
Maciej Suminski 9951521212 vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements. 2014-09-30 15:59:46 +02:00
Maciej Suminski e352bea476 vhdlpp: Support for variable declarations in subprograms.
Fixes sorrymsg: "variable_declaration not supported."
2014-09-30 15:58:13 +02:00
Maciej Suminski a63289c2fc vhdlpp: VTypeArray::range_t handles direction (to/downto). 2014-09-15 12:10:04 +02:00
Maciej Suminski c92dea77fc vhdlpp: Basic support for unbounded array types.
Once a signal/variable of unbounded array type becomes limited in its size, it
is emitted as a packed array. Therefore currently it works only for
bit/logic/reg/wire types.
2014-08-15 10:21:45 +02:00
Maciej Suminski 5ed60a151f Added support for real type in vhdlpp. 2014-08-06 15:00:35 +02:00
Martin Whitaker 9e25884f12 Fix for br942 - allow function declaration in VHDL architecture. 2013-12-11 23:00:58 +00:00
Cary R 07cc18284c Fix print token/argument mismatches and other cppcheck fixes 2013-09-09 13:34:38 -07:00
Stephen Williams ca9616dc7b Better simple_expression parse rules. 2013-06-12 14:21:36 -07:00
Stephen Williams 24bd630cb2 Parse (to sorry messages) unbounded array definitions. 2013-06-12 14:21:36 -07:00
Stephen Williams dca6171f5f SV emit function ports in package subprograms. 2013-06-12 14:09:07 -07:00
Stephen Williams e927960121 Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
Stephen Williams d9fea802da Function declarations in packages
This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
Stephen Williams bad8ed39c1 Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
Stephen Williams 5651e6e001 Improve error handling. 2012-11-02 19:30:12 -07:00
Stephen Williams 7fad717a1e Redesign selected_name rule to better handle complex prefixes
Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
2012-09-03 16:00:10 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Cary R 1749d10966 Fix some clang/bison compile warnings. 2012-08-06 15:49:11 -07:00
Larry Doolittle befff82655 Spelling fixes
Comments and debug messages.
2012-07-27 18:25:32 -07:00
Stephen Williams 4748f0cb5e Handle incomplete type declarations
Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
2012-05-22 17:31:27 -07:00
Stephen Williams 63b7fe059d Reword concat to handle aggregate arguments.
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
Stephen Williams a5458828cd Some vhdl parser error handling. 2012-05-22 17:31:26 -07:00
Stephen Williams 7eb89c5548 Parse name prefix syntax for record member reference.
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
Stephen Williams 1249b5dd32 Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
Stephen Williams 9ed56a6354 Parse record types, and some new aggregate types. 2012-05-22 17:31:25 -07:00
Cary R aedbda5a75 Identifiers need to be deleted with delete[]
This patch fixes a mismatch in the delete style.
2011-12-18 16:45:08 -08:00
Stephen Williams 2063c5ee9d Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
Stephen Williams 98d928f6e0 Add support for VHDL for-generate 2011-10-30 17:10:19 -07:00
Stephen Williams 15da45f7cb VHDL initialization expressions for signals. 2011-10-29 17:06:40 -07:00
Stephen Williams 4f98a6d181 Rewire VHDL addition expression parsing.
The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
Stephen Williams 2be682f8a5 Support VHDL component instantiations with generics as Verilog parameters. 2011-10-23 17:08:48 -07:00
Stephen Williams d9acfe57b1 Put off array bound evaluation / describe entity generics as parameters
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.

Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
Stephen Williams a6f63b8a54 Parse generic clause in entity headers
The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
2011-10-15 09:49:24 -07:00
Stephen Williams 6268db6e68 Handle simple type declarations. 2011-10-09 15:25:35 -07:00
Stephen Williams 271aaf6376 Parse enumeration type declarations. 2011-10-01 17:04:04 -07:00
Stephen Williams 8003382b3e Elaborate and emit case statements. 2011-10-01 11:45:28 -07:00
Stephen Williams 88cce86c63 Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
Stephen Williams 677a22d353 Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
Stephen Williams 4d445dc269 Fix parse of unnamed processes. 2011-09-18 09:37:11 -07:00
Stephen Williams 3497e2e663 Distinguish bit selects of entity ports from function calls.
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
Stephen Williams 6d28c989ce Handle the basics of aggregate expressions
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
Stephen Williams 4464c5849b Handle a few built-in functions internally.
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
Stephen Williams 7556a37859 Parse function calls, and detect type case expressions.
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.

Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
Stephen Williams f5220c54f1 Handle variables in process statements
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
Stephen Williams f2629d53a2 Add VHDL support for named libraries
Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
2011-07-30 15:04:07 -07:00
Cary R de356b03c8 Fix most of the cppcheck warnings in the vhdlpp directory.
Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
Cary R 836e61e878 Fix spacing issues in the code.
Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
Stephen Williams 116d9f5f54 Merge branch 'master' into work7 2011-07-24 11:06:22 -07:00
Pawel Szostek 50f7e1b69e Add parser cleanup to vhdlpp
This commit adds removal of global objects in
the execution of vhdlpp. This includes deleting
design entities and the global parse scope.
2011-07-24 10:03:03 -07:00
Pawel Szostek 3764216a88 Use stl stack for for carrying scopes
This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
2011-07-24 09:50:31 -07:00
Pawel Szostek 21008f2ba9 Add missing or fix existing deletes in VHDL parser
Thanks to valgrind analysis it turned out that
there were objects in the parser that were not being
deleted in a proper way. This patch fixes them all.
2011-07-24 09:47:41 -07:00
Stephen Williams df8efed22b Parse work library for imported packages
When a "use" clause tries to pull a package from the work library,
put together a file name and try to find that package in the
work library directory. If found, parse the package file and
try again to find the package.
2011-07-23 10:07:20 -07:00
Stephen Williams 3ef1d01ad1 Rework parse/lex API to be reentrant
Bison and Flex generate different interfaces for reentrant
parsers, so handle that different API. We need this change
because library support is going to reuse the parser to
read in library packages.
2011-07-22 20:49:57 -07:00
Pawel Szostek 60deb775ca Add support for VHDL's loop statements 2011-07-12 19:20:04 -07:00
Pawel Szostek b376115e15 Add parser support for VHDL's null statements
Handle null statements in sequences of statements.
If a null is encountered, it is omitted and not
added to the list of statements.
2011-07-08 18:14:00 -07:00
Pawel Szostek ad31eaaea8 Add parser support for VHDL's procedure call
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
Pawel Szostek 721f9d5d9b Add String Expression to the VHDL parser 2011-07-08 18:05:06 -07:00
Pawel Szostek 88760b9982 Fix case-when VHDL statement 2011-07-08 17:59:55 -07:00
Pawel Szostek 5934dcc17c Add parser support for vhdl's case-when
Case-when statements are now recognized and
turned into corresponding objects. Elaboration
and emission is still not done.
2011-06-30 19:57:27 -07:00
Pawel Szostek bff0927db0 Add remaining tokens to vhdl lexor 2011-06-30 19:36:24 -07:00
Stephen Williams 41601696cc properly handle vhdl open ports in component instantiations. 2011-06-12 16:59:07 -07:00
Stephen Williams bf40c8ecc5 Conditional statements and expressions
Elaborate and emit a variety of conditional constructs.
Fix up type handling for some expression types
Elaborate continuous signal assignments.
2011-06-12 10:51:31 -07:00
Stephen Williams 2e28782af3 Add parser support for concatenations/conditional assignment/elsif
Some of these should be easy to translate, but get the parsing out
of the way first.
2011-06-05 13:58:54 -07:00
Stephen Williams fc25ccde06 Basic emit of sequential code
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
2011-05-15 11:07:42 -07:00
Stephen Williams 3e419dc854 Parse/decorate sequential statements.
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.

Also add a few missing expression types.
2011-05-08 16:40:35 -07:00
Stephen Williams 7afd4210db Parse some sequential statements and processes. 2011-05-08 13:51:21 -07:00
Cary R 12df29af55 Fix space issues.
Thsi patch removes space before end of line, etc.
2011-04-20 17:26:52 -07:00
Stephen Williams 3ff7a8f7b0 Add support for constants and package types.
Significant rework of scope management to unify the handling of
types in the ieee library and types/constants/components in packages.
This involved adjusting the parser rules to manage a stack of scopes
and rewriting the IEEE library support to not use global maps for
the loaded types.
2011-04-17 17:19:09 -07:00
Stephen Williams 303f057de1 Support collecting ALL component declarations from a used scope. 2011-04-13 19:55:18 -07:00
Stephen Williams d4c5cfc584 Add packages and component declarations within those packages.
This creates the Package class to represent packages, and the
Scope class to represent scopes in general. The library functions
are worked up to support scanning scopes for declarations that are
imported by "use" clauses.
2011-04-13 18:30:00 -07:00
Stephen Williams 791adfab68 Check ports match up in component instantiations.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
2011-04-10 09:42:22 -07:00
Pawel Szostek 9bdc040520 Add missing ``sorry'' messages in VHDL parsing 2011-04-02 09:30:36 -07:00
Pawel Szostek cef37e0a4b Add component specification parsing
A class for component specification has been added
2011-04-02 09:29:42 -07:00
Pawel Szostek 830b7cf122 Add basic instantiation list handling in VHDL
A class for representing instantiation list has
been added.
2011-04-02 09:27:58 -07:00
Pawel Szostek 2af35040cc Fix constructs sequence in bison file for VHDL 2011-04-02 09:24:34 -07:00
Pawel Szostek 26e6865bef Add entity aspects to VHDL parsing
Entity aspects are now recognized and parsed
into corresponding objects. A new class (entity_aspect)
has been added.
2011-04-01 17:03:45 -07:00
Stephen Williams abb03632dd Basic elaboration of vhdl component instantiations.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
2011-03-31 19:07:43 -07:00
Pawel Szostek 37d6de344d Add use clause parsing
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.

Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
2011-03-31 18:57:25 -07:00
Stephen Williams 162b26c101 Add more complete support for vhdl local signals.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.

In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).

I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
2011-03-28 14:34:02 -07:00
Pawel Szostek f057ce0859 Basic VHDL configuration parsing
The bison grammar has been extended in order
to parse configuration statements. Parsing
remains very primitive but principal constructs
can be now recognized.
2011-03-28 14:29:06 -07:00
Pawel Szostek ce5c263b4a Simplify entity parsing (removed the duplicate code) 2011-03-23 11:59:02 -07:00
Stephen Williams 8580ceea4d Parse component declarations / parse signal declarations.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.

Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
2011-03-22 09:18:20 -07:00
Stephen Williams 89aa08e1aa Add parser support for architecture declaratives and component instantiations
Also include support for "sorry" messages so that we have a place
to hang unsupported but properly parsed constructs.

In the process of doing this, I also encountered and add parser support
for indexed names. And matching "sorry" messages.
2011-03-22 09:18:01 -07:00
Stephen Williams 2b7323f2c2 Support vhdl identifier lists in interface elements.
syntax like this is ok:

  name1, name1, name3 : in bit;
  name4 : out bit;

and so on.
2011-03-22 09:17:40 -07:00