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43 Commits

Author SHA1 Message Date
Stephen Williams 24b64365a6 Better handling of root selection for BLIF target. 
There is now an implicit $unit package that needs to be ignored by
the blif target. Take this opportunity to make the root module checking
for the blif target a bit more robust.
 2022-02-27 18:11:00 -08:00
Cary R 1d318c4393 Update cppcheck to not run posix and add some -U flags 2021-01-02 13:23:59 -08:00
Cary R fb237fb006 Update the user visible copyright to be 2020 2020-05-31 13:41:38 -07:00
Huang Rui 11001f58d5
Thoroughly fix parallel installation issues 
In PR #300, @xdch47 pointed out a stable way to fix parallel
installation problems.

This fix applied the method, thanks!

Signed-off-by: Huang Rui <vowstar@gmail.com>
 2020-02-12 22:42:04 +08:00
Huang Rui 93d2aa03d6 [14/20]tgt-blif/Makefile.in:Remove useless $(INSTALL_DOC) 
fix install timestamp check and Remove useless $(INSTALL_DOC)

Fix bug: https://bugs.gentoo.org/705412
Fix bug: https://github.com/gentoo/gentoo/pull/14096
Related: https://github.com/steveicarus/iverilog/pull/294

Signed-off-by: Huang Rui <vowstar@gmail.com>
 2020-02-12 22:08:40 +08:00
Cary R ea4e41207c Update cppcheck standards that are checked 2019-09-30 22:14:15 -07:00
Yury Gribov 2d7534b005 Implement barrel shifter LPM for BLIF target 2016-06-13 10:55:38 -07:00
Yury Gribov 31482cbceb Implement sign extension LPM for BLIF target 2016-06-13 10:51:46 -07:00
Yury Gribov 2d5a48c579 Support PULLUP/DOWN and BUFZ in BLIF backend 2016-06-13 10:26:46 -07:00
Christian Taedcke 6d5aabd4f0 Make a few constructors explicit. 
This removes cppcheck warnings.
 2015-10-22 12:33:33 +02:00
Larry Doolittle b23faff27c Just a few more spelling fixes 
Includes some user-visible messages
 2015-06-17 08:09:34 -07:00
Cary R 9b1de4b038 Call IEEE 1800 SystemVerilog 2014-09-08 20:49:40 -07:00
Cary R d6b6b76015 Update header files to use a more standard name to prevent rereading 
This is from github report #16. There are likely a few more issues
that need to be addressed though this takes care of the major ones.
 2014-07-23 13:42:56 -07:00
Cary R 0ffd61a835 Remove some cppcheck warnings 2014-06-28 16:56:09 -07:00
Larry Doolittle 77a01f65d0 Remove fixable unused-parameter warnings 
I see other warnings within vhdlpp/lexor.cc caused by a flex bug
(see http://sourceforge.net/p/flex/bugs/115/), which I won't try to work around.
 2014-01-30 15:34:08 -08:00
Cary R bf9781e8fd In tgt-blif the code must be linked with the C++ compiler 2013-12-06 15:09:56 -08:00
Cary R 5a0f9f4604 Fix CXX variable in tgt-blif/Makefile.in 2013-12-03 10:12:08 -08:00
Cary R 8616e3d6fa Fix space/tab problem. 2013-09-23 10:32:54 -07:00
Stephen Williams 9b3987bf3c blif target supports wide LPM_PART_VP devices. 2013-08-31 16:43:37 -07:00
Stephen Williams 1b79df810f Handle DFF with clock-enable in blif code generator 
In the ASIC universe, it is (probably) OK to replace a DFF CE
with a mux of the D input with the Q output. The idea is that
if the CE is true, the DFF latches D, but if CE is false, the DFF
re-latches the current output.
 2013-08-25 12:27:57 -07:00
Stephen Williams 9dde4b705d Detect and synthesize FF clock enables. 
Too bad BLIF doesn't support 'em.
 2013-08-25 12:27:57 -07:00
Stephen Williams d209d8ee39 blif support for IVL_LPM_FF devices. 2013-08-25 12:27:56 -07:00
Stephen Williams 6b5ae5e4db Force calculation of blif_nex_data_t width for lib_mux_s1 devices. 2013-08-25 12:27:56 -07:00
Stephen Williams a6fb6be8b5 blif code generator support for arbitrary MUX devices. 2013-08-25 12:27:56 -07:00
Stephen Williams 947d642da7 Always turn on ivl synthesis for blif target. 2013-08-25 12:27:55 -07:00
Stephen Williams 11be93ce55 Merge branch 'master' of github.com:steveicarus/iverilog 2013-08-12 19:50:52 -07:00
Stephen Williams aaf35ca6ab Fix blif handling of wide ligic gates. 2013-08-12 19:50:32 -07:00
Cary R b983d5546b Fix cppcheck call in tgt-blif (use .cc instead of .c) 2013-08-12 16:35:45 -07:00
Cary R 7c0a75cf0c tgt-blif is C++ so use the extra C++ warning flags 2013-08-06 17:10:52 -07:00
Cary R f054500fe2 Fix space issues in tgt-blif 2013-08-06 17:09:37 -07:00
Stephen Williams 6684b2db04 Add BLIF support for ternary (MUX) operators. 2013-08-01 17:28:04 -07:00
Stephen Williams 999a53ab75 Add blif LIB_RE_* gates support. 2013-08-01 17:28:04 -07:00
Stephen Williams 534d44ba55 blif support for bit selects. 2013-08-01 17:28:04 -07:00
Stephen Williams c7c10613d7 blif support for unsigned magnitude comparison. 2013-08-01 17:28:04 -07:00
Stephen Williams dfc44db0ef BLIF support for IVL_LPM_CMP_EQ and IVL_LPM_CMP_NE 2013-08-01 17:28:04 -07:00
Stephen Williams 7a6192b5c8 Generate blif code for IVL_LPM_SUB device. 2013-08-01 17:28:04 -07:00
Stephen Williams 05f90bcf55 Support blif emit of IVL_LPM_ADD device. 2013-08-01 17:28:04 -07:00
Stephen Williams e709849243 Add a README-BLIF.txt file for the blif target. 2013-08-01 17:28:04 -07:00
Stephen Williams 1b2fa39cdc Add some more basic logic gates to blif target. 2013-08-01 17:28:04 -07:00
Stephen Williams b4ec36ec78 blif nex_data_t collects name data early. 
It is possible for the get_name_index() method to be called before
the get_name() method, so need to handle that case.
 2013-08-01 17:28:04 -07:00
Stephen Williams dddaacc6fd Follow non-canonical bit numbering. 
The signal bit numbering should be used for signals. This is
necessary for .model ports because the user specified numbers
are part of the interface, but once that is done, it is trivial
to follow it internally as well.
 2013-08-01 17:28:03 -07:00
Stephen Williams e0c9efd129 Implement blif support for constants and some logic/lpm gates. 
This starts the handling of various logic gates.
 2013-08-01 17:28:03 -07:00
Stephen Williams d2034a6458 Initial BLIF code generator. 
Add the -tblif code generator target, and include some basic
useful behavior.
 2013-08-01 17:28:03 -07:00