Commit Graph

168 Commits

Author SHA1 Message Date
steve 41f9a84a4b Handle much more complex event expressions. 1999-05-01 02:57:52 +00:00
steve 4b73655537 Generate SubSignal refrences in vvm. 1999-04-25 22:52:32 +00:00
steve d3350c9b27 Add to vvm proceedural memory references. 1999-04-22 04:56:58 +00:00
steve 5895d3c98d Add memories to the parse and elaboration phases. 1999-04-19 01:59:36 +00:00
steve b7f833dd71 Support more operators, especially logical. 1999-03-15 02:43:32 +00:00
steve a2bc27318f Handle default case. 1999-02-22 03:01:12 +00:00
steve e5f5f41515 Elaborate gate ranges. 1999-02-15 02:06:15 +00:00
steve fef81958bc Do not generate code for signals,
instead use the NetESignal node to
 generate gate-like signal devices.
1999-02-08 03:55:55 +00:00
steve 30a3953c85 Turn the NetESignal into a NetNode so
that it can connect to the netlist.
 Implement the case statement.
 Convince t-vvm to output code for
 the case statement.
1999-02-08 02:49:56 +00:00
steve d1e2b036fc Add startup after initialization. 1999-01-01 01:46:01 +00:00
steve 63a8b4abe2 Function to calculate wire initial value. 1998-12-20 02:05:41 +00:00
steve 4e2c0036aa VVM support for small sequential UDP objects. 1998-12-17 23:54:58 +00:00
steve af8d6fbf01 NetAssign handles lvalues as pin links
instead of a signal pointer,
 Wire attributes added,
 Ability to parse UDP descriptions added,
 XNF generates EXT records for signals with
 the PAD attribute.
1998-11-23 00:20:22 +00:00
steve 7859de1e4e Add support it vvm target for level-sensitive
triggers (i.e. the Verilog wait).
 Fix display of $time is format strings.
1998-11-10 00:48:31 +00:00
steve ebad845fc3 Add procedural while loops,
Parse procedural for loops,
 Add procedural wait statements,
 Add constant nodes,
 Add XNOR logic gate,
 Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
steve 47a444fb92 Calculate expression widths at elaboration time. 1998-11-07 19:17:10 +00:00
steve b118634189 Handle procedural conditional, and some
of the conditional expressions.

 Elaborate signals and identifiers differently,
 allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00