dfbca0b186
vhdlpp: Emit use_types in Architecture.
2014-10-17 14:13:06 +02:00
4a779f43bd
vhdlpp: Fix error message for 'right attribute.
2014-10-17 14:13:06 +02:00
97df6183a9
vhdlpp: Emit '-' std_logic value as 'x'.
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Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
f36bebf0e1
Remove some compile warnings.
2014-10-13 16:31:53 -07:00
3fd622e4eb
vlog95: Add support for emitting global tasks and functions
2014-10-13 09:51:55 -07:00
da4200c5bd
Update lz4 files to the latest from GTKWave
2014-10-13 09:44:57 -07:00
712f394224
Elaborate classes in packages.
2014-10-10 18:53:53 -07:00
d6685f40a1
Merge pull request #46 from orsonmmz/range
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VHDL attributes: 'range, 'reverse_range, 'left & 'right
2014-10-10 17:23:59 -07:00
9ff9cbf4aa
vhdlpp: Smarter determining the direction in for loops.
2014-10-10 18:39:14 +02:00
a992f3ce7c
vhdlpp: Evaluation for 'left and 'right attributes.
2014-10-10 18:35:17 +02:00
1a4edcac48
vvp: Accepts continuous assignment for 2-state nets.
2014-10-10 16:16:46 +02:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
7f6100be2a
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
2014-10-09 10:29:14 +02:00
4b60d2737e
vhdlpp: Skip signed & unsigned in types dump in packages.
2014-10-09 10:28:35 +02:00
c7beef907d
vhdlpp: Support for 'range and 'reverse_range attributes.
2014-10-08 11:18:06 +02:00
44da7de651
vhdlpp: prange_t may have the direction determined automatically.
2014-10-08 10:26:37 +02:00
6887c82540
vhdlpp: Added ExpAttribute::write_to_stream().
2014-10-08 10:21:03 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fddb3ec129
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.
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Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
2014-10-07 14:25:00 +02:00
bfafd175fa
Fix parse.y bad handling of file names in some situations.
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The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
2014-10-02 19:42:48 -07:00
23238aa7ac
Handle functions in $root scope.
2014-10-02 15:04:14 -07:00
2397aa1587
Merge pull request #45 from orsonmmz/subprogram
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Subprograms
2014-10-02 14:14:52 -07:00
b4119de9b1
Merge branch 'master' of github.com:steveicarus/iverilog
2014-10-02 14:10:10 -07:00
338a0eb11a
Get $root scope tasks/fuctions down to the ivl_target API.
2014-10-02 14:09:27 -07:00
fde6525acb
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
2014-10-01 14:56:32 +02:00
c5fee8bdb9
Elaborate root tasks/functions.
2014-09-30 16:06:32 -07:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
9e856810b9
vhdlpp: Workaround to avoid translation of variables to wires in functions.
2014-09-30 15:59:45 +02:00
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
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VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
e352bea476
vhdlpp: Support for variable declarations in subprograms.
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Fixes sorrymsg: "variable_declaration not supported."
2014-09-30 15:58:13 +02:00
747e656a0e
vhdlpp: Added ScopeBase::transfer_from() method.
2014-09-30 15:00:55 +02:00
7b5470c8a7
vhdlpp: Subprogram class inherits from ScopeBase.
2014-09-30 15:00:55 +02:00
985a3eb206
Update lz4 files to the latest from GTKWave
2014-09-26 15:04:55 -07:00
e1ec27e18c
Merge pull request #43 from orsonmmz/record_elab
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Elaboration & emit functions for aggregate expressions used as record initializers.
2014-09-18 12:59:28 -07:00
d13e488f4c
Merge pull request #42 from orsonmmz/const_package
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Enable constant initializers that require elaboration in packages.
2014-09-18 12:58:19 -07:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
94abef195a
vhdlpp: Commented out named assignment for records.
2014-09-17 16:30:44 +02:00
54696e0127
vhdlpp: Elaboration & emit support for aggregate initializer expressions in records.
2014-09-17 11:24:16 +02:00
d85096c56a
Add support for implict this in class methods
2014-09-16 17:08:57 -07:00
d16a9dcfc6
Add support for calling a class function method using this/super
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Also standardize the parser code that uses this/super.
2014-09-16 12:25:14 -07:00
9842035d89
vhdlpp: Simplified the initalization for signals/variables.
2014-09-16 16:31:18 +02:00
480668fee6
Add support for classes defined in $root scope.
2014-09-15 17:37:30 -07:00
fa21527e9f
Classes in $root scope up to elaboration.
2014-09-15 17:37:30 -07:00
98799ff7fa
Allow class properties to be arrayed.
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This adds the runtime support for class properties that are classes
to be arrayed. Add a means to define the dimensions of a property
in the vvp format, and add functions for setting/extracting elements
of a property.
2014-09-15 17:37:30 -07:00
ea4b000be6
Get arrayed property expressions down to the ivl_target API.
2014-09-15 17:37:30 -07:00
e330a0bd6e
vhdlpp: Corrected VTypeArray::write_to_stream().
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Now it outputs "typedef(range)" instead of "array (range) of type".
2014-09-15 12:10:05 +02:00
Maciej Suminski
Cary R
Stephen Williams