a1ad6d4b51
Support IVERILOG_VPI_MODULE_PATH environment variable
2018-10-28 12:44:09 -07:00
a638d1eed0
Check for too many paths specified and fix path priority so paths specified on command line supersede built-in paths
2018-10-28 12:43:40 -07:00
5aae9ea770
Fix bit width when converting real value to binary/hex string in VPI.
2018-10-07 17:17:33 +01:00
3e25b04685
SIGHUP is not available in Windows.
2018-10-06 21:07:13 +01:00
f1608e163f
Fix implicit fallthrough warnings when building with recent GCC.
2018-10-06 20:15:42 +01:00
542fe2cf77
Enable checks for VPI const-correctness.
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Note we only want these enabled when building the compiler and runtime
binaries. If we included the ICARUS_VPI_CONST definition in the global
CPP_FLAGS, that would propagate to the flags used by iverilog-vpi, so
would affect compilation of user VPI code.
2018-10-06 11:48:19 +01:00
603ff303f5
Cleanly terminate vvp on SIGHUP or SIGTERM (GitHub issue #203 ).
2018-09-29 23:25:04 +01:00
11c826216a
Fix for GitHub issue #198 - support octal display for thread variables.
2018-06-12 22:58:07 +01:00
7ad5b59a6f
Fix for GitHub issue #199 : handle signed division overflow.
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When performing a signed division or modulus operation using native
arithmetic, trap the special case that the numerator is the minimum
integer value and the denominator is -1, as this gives an undefined
result in C++.
2018-06-12 21:59:58 +01:00
6e49ab10ec
Further fix for br1029.
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The code in vpi_callback.cc is replicated in vpi_vthr_vector.cc,
so we have to replicate the fix. This should really be factored
out.
2018-05-14 22:14:51 +01:00
5a4e99b0e8
Fix br1029 - correct rounding when vpi_get_value converts real to integer string.
2018-05-12 23:49:11 +01:00
5cfb7d68ae
Add support for rtran switches in vvp.
2018-02-23 22:30:32 +00:00
36eef5154f
Implement supply->strong strength reduction for non-resistive switches.
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As specified in 1364-2005 section 7.11.
2018-02-23 22:07:59 +00:00
24a4ec3bb2
Hide the always_comb/latch TO event by not attaching it to a scope.
2018-01-01 21:19:58 -08:00
0caa109174
Merge pull request #181 from phire/portinfo_grammar
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vvp grammar: .port_info statements should require/generate semicolons.
2017-12-18 10:04:42 -08:00
d01e5accc0
vpp: Require semicolon after .port_info statements
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Optional until 12.0
2017-12-17 00:06:09 +13:00
db1ea05452
Fix #0 to trigger in the inactive region and add a trigger for always_comb/latch
2017-12-03 20:17:42 -08:00
3fc9ad2db0
Add support for the wild compare operators ==? and !=?
2017-11-17 19:32:50 -08:00
f03033e612
Update flex destroy routines to work for version 2.6 and greater
2017-11-16 19:11:50 -08:00
ad83a135e5
Fix assertion failure in vvp wide functor.
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If the functor output is read before any values have propagated to
the functor inputs, the internal storage won't have been initialised.
2017-11-08 20:35:18 +00:00
c622d372f9
Fix for GitHub issue #169 : nets can get given wrong scope in VPI.
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In vvp, the __vpiSignal object holds a pointer to the scope containing
the signal. This was getting set to the current scope when the net was
finally resolved, rather than to the scope where the net was declared.
2017-11-07 18:48:48 +00:00
d9478bd837
Update cppcheck waiver files
2017-10-23 00:21:51 -07:00
5ca058bfb5
Add support for darray initialisation from another darray.
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Fixes GitHub issue #164 .
2017-10-08 17:51:33 +01:00
e315cafa01
Fix for GitHub issue #165 : assertion failure on thread join.
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If a thread becomes detached due to a join_any statement, that
thread must not attempt to join its parent, even if the parent
is waiting on a subsequent join statement.
2017-10-07 16:41:26 +01:00
a1a7f5deff
Fix error in last commit.
2017-09-17 19:58:13 +01:00
0bed890bc6
Fix use after free bug in vvp when a task or function is disabled.
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Use test_joinable() and do_join() to ensure everything gets cleaned
up before the thread is reaped. This should fix br1016, br1017, and
br1018.
2017-09-17 19:48:54 +01:00
ac87138c44
Fix for br1019 - allow multiple array words to be attached to a vpi callback.
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Normally there is at most one signal attached to a vvp functor, but
due to port collapsing, there can be more than one. If these signals
are array words, we need to trigger vpi callbacks on all the associated
arrays when the functor value changes.
2017-08-12 12:23:43 +01:00
62e0f59b07
No need for class in previous patch
2017-06-19 21:26:24 -07:00
10ef0eb109
Fix class versus struct warning in clang
2017-06-19 21:26:16 -07:00
e2be64558b
Ensure value passed to named event via vpi_put_value() is initialised.
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The __vpiNamedEvent::vpi_put_value() function ignores the value, but
intermediate code looks at it.
2017-06-15 09:11:11 +01:00
3de7c234f7
Implement vpi_put_value() for named events (GitHub issue #158 ).
2017-06-15 08:47:29 +01:00
c79df7c44b
fix failing VPI callbacks the vpip_cur_task was left dangling
2017-01-01 17:44:54 -08:00
0fdf29e099
Fix for GitHub issue #117 - delays in VPI simulation time callbacks.
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Change cbReadWriteSynch and cbReadOnlySynch to interpret the passed
time value as a relative delay, not an absolute time. This matches
the behaviour of other simulators.
2016-09-25 20:43:58 +01:00
e56e52bc42
Merge branch 'master' of github.com:steveicarus/iverilog
2016-09-19 12:59:41 -07:00
f32b64f497
Fixed warnings about shifting a negative value
2016-09-19 12:54:15 -07:00
5853e32f82
Fix some cppcheck warning issues
2016-09-13 23:45:25 -07:00
d44c814bab
Remove .alias records from vvp generated code.
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Net arrays can be handled by nets directly, instead of creating
.alias records.
2016-08-31 14:05:09 -07:00
a2fbdeff78
Add some pass by reference to vvp
2016-08-14 22:26:16 -07:00
ad5a7f7ca3
Update cppcheck vvp suppression file
2016-08-14 21:18:55 -07:00
d0e0776910
Make the base class match the derived classes regarding passing by reference
2016-08-14 21:18:44 -07:00
7bed181f68
Support timescales in design units that aren't inside a module.
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SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
43cd693fe0
Put start events to proper queue.
2016-07-17 09:47:08 -07:00
9ad46044b4
Cleanup
2016-06-30 17:47:34 +02:00
8234f1845d
Fix for GitHub issue #106 - prevent VPI writes during read-only synch.
2016-06-09 21:27:20 +01:00
61c82d2cb0
Handle mixed continuous and non-blocking assignments to same vector.
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SystemVerilog allows a mixture of procedural and continuous assignments
to be applied to different parts of the same vector. The previous attempt
to make this work for non-blocking assignments was flawed (see preceding
fix for vvp_fun_part_pv::recv_vec4_pv). Instead, handle this case by
converting the non-blocking assignment into a delayed force statement,
which matches the way mixed continuous and blocking assignments are
handled.
2016-05-10 22:16:40 +01:00
0c66116f51
Fix for GitHub issue #103 - vvp assertion failure on part select propagation.
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The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.
2016-05-10 21:59:21 +01:00
6e5ed73b09
Extended fix for GitHub issue #99 .
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Most vvp functors need to support recv_vec4_pv. Any that are strength-aware
also need to support recv_vec8_pv. Note the simplifying assumption that is
documented in the base class recv_vec4_pv_ implementation.
2016-04-18 23:47:43 +01:00
b2f7d09f0d
Fix GitHub issue #99 - recv_vec4_pv not implemented for arithmetic functors.
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Also initialise the stored operand values to 'bz instead of 'bx to get
the correct results when bits are not driven.
2016-04-04 22:29:54 +01:00
4521be4510
More spelling, comments only
2016-04-01 11:02:34 -07:00
89edf62206
Capitalize Verilog in a few places
2016-04-01 11:02:24 -07:00
Alex Forencich
Martin Whitaker
Cary R
Stephen Williams
Scott Mansell
Johann Klammer
Maciej Suminski
Yury Gribov
Michele Castellana
Larry Doolittle