962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
777e7e0a3d
vhdlpp: Added ExpFunc::func_ret_type() method.
2015-02-04 16:57:43 +01:00
839f9cd7ae
vhdlpp: Added ReturnStmt::cast_to() method.
2015-02-04 16:57:43 +01:00
b8b2f53027
vhdlpp: Added VType::get_generic_typename() method.
2015-02-04 16:57:43 +01:00
9b3bd039bb
vhdlpp: Added ExpCast class.
2015-02-04 16:57:42 +01:00
51b9191021
vhdlpp: Added VType::is_unbounded() method.
2015-02-04 16:57:42 +01:00
ff5b696569
vhdlpp: Improved SequentialStmt visitor.
2015-02-04 16:02:38 +01:00
b05a19dffc
vhdlpp: VTypeArray emits dimensions in a bit smarter way.
2015-02-04 16:02:38 +01:00
e6b22a2bea
vhdlpp: Visitor for SequentialStmt.
2015-02-04 16:02:38 +01:00
0592ba042e
vhdlpp: For-loop emission rewritten to handle 'range in subprograms.
2015-02-04 16:02:38 +01:00
6fd10dedb6
Add some implicit support for std and textio libraries
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Patch submitted by Fabrizio Ferrandi.
2014-12-18 08:20:19 -08:00
2e8c4e3dbc
Basic patch from github #44
2014-11-04 11:39:01 -08:00
c55a013162
vhdlpp: Support for integer() function.
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Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd )
Real numbers are rounded, this is compatible with ModelSim behavior.
2014-10-17 14:53:59 +02:00
dfbca0b186
vhdlpp: Emit use_types in Architecture.
2014-10-17 14:13:06 +02:00
4a779f43bd
vhdlpp: Fix error message for 'right attribute.
2014-10-17 14:13:06 +02:00
97df6183a9
vhdlpp: Emit '-' std_logic value as 'x'.
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Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
9ff9cbf4aa
vhdlpp: Smarter determining the direction in for loops.
2014-10-10 18:39:14 +02:00
a992f3ce7c
vhdlpp: Evaluation for 'left and 'right attributes.
2014-10-10 18:35:17 +02:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
7f6100be2a
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
2014-10-09 10:29:14 +02:00
4b60d2737e
vhdlpp: Skip signed & unsigned in types dump in packages.
2014-10-09 10:28:35 +02:00
c7beef907d
vhdlpp: Support for 'range and 'reverse_range attributes.
2014-10-08 11:18:06 +02:00
44da7de651
vhdlpp: prange_t may have the direction determined automatically.
2014-10-08 10:26:37 +02:00
6887c82540
vhdlpp: Added ExpAttribute::write_to_stream().
2014-10-08 10:21:03 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fddb3ec129
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.
...
Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
2014-10-07 14:25:00 +02:00
fde6525acb
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
2014-10-01 14:56:32 +02:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
9e856810b9
vhdlpp: Workaround to avoid translation of variables to wires in functions.
2014-09-30 15:59:45 +02:00
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
...
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
e352bea476
vhdlpp: Support for variable declarations in subprograms.
...
Fixes sorrymsg: "variable_declaration not supported."
2014-09-30 15:58:13 +02:00
747e656a0e
vhdlpp: Added ScopeBase::transfer_from() method.
2014-09-30 15:00:55 +02:00
7b5470c8a7
vhdlpp: Subprogram class inherits from ScopeBase.
2014-09-30 15:00:55 +02:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
94abef195a
vhdlpp: Commented out named assignment for records.
2014-09-17 16:30:44 +02:00
54696e0127
vhdlpp: Elaboration & emit support for aggregate initializer expressions in records.
2014-09-17 11:24:16 +02:00
9842035d89
vhdlpp: Simplified the initalization for signals/variables.
2014-09-16 16:31:18 +02:00
e330a0bd6e
vhdlpp: Corrected VTypeArray::write_to_stream().
...
Now it outputs "typedef(range)" instead of "array (range) of type".
2014-09-15 12:10:05 +02:00
cb03802a17
vhdlpp: Added VTypeArray::basic_type() to cope with
...
arrays based on typedefs.
2014-09-15 12:10:05 +02:00
22d18cb28d
vhdlpp: Typedefs in packages are emitted before constants.
2014-09-15 12:10:04 +02:00
c98c3e5d14
vhdlpp: Inlined a few functions.
2014-09-15 12:10:04 +02:00
a63289c2fc
vhdlpp: VTypeArray::range_t handles direction (to/downto).
2014-09-15 12:10:04 +02:00
251b75003f
vhdlpp: Skip writing '=>' for ExpAggregates if there are no fields specified.
2014-09-15 12:10:04 +02:00
01b4d49d4a
vhdlpp: Do not emit constants from packages.
...
They are elaborated and emitted by architectures that make use of packages.
2014-09-15 12:10:04 +02:00
f851fc6981
vhdlpp: Fixed ExpAggregate::write_to_stream().
2014-09-15 12:10:04 +02:00
a25cde3bc7
vhdlpp: Added ExpString::write_to_stream().
2014-09-15 12:10:04 +02:00
Maciej Suminski
Stephen Williams
Cary R