iverilog

Commit Graph

Author	SHA1	Message	Date
Nick Gasson	2115e87f78	Fix VHDL naming collisions with modules This fixes a bug where the renaming rules for modules would generate entity names that collided with already existing module names.	2009-02-05 14:40:47 -08:00
Nick Gasson	babc9c1352	Various signal naming fixes for VHDL target This avoids generating invalid VHDL signal names in the following cases: - The name begins or ends with an underscore - The name contains two consecutive underscores - The name is the same as a component declaration - The name differs from another only in case	2009-01-28 17:44:14 -08:00
Nick Gasson	f1f9274bb9	Move VHDL global state management to a single file The new state.cc/hh file now manages all the global state that we maintain while generating VHDL. This should make the code a bit tidier.	2009-01-17 09:19:58 -08:00

Author

SHA1

Message

Date

Nick Gasson

2115e87f78

Fix VHDL naming collisions with modules

This fixes a bug where the renaming rules for modules
would generate entity names that collided with already
existing module names.

2009-02-05 14:40:47 -08:00

Nick Gasson

babc9c1352

Various signal naming fixes for VHDL target

This avoids generating invalid VHDL signal names in the
following cases:
	- The name begins or ends with an underscore
	- The name contains two consecutive underscores
	- The name is the same as a component declaration
	- The name differs from another only in case

2009-01-28 17:44:14 -08:00

Nick Gasson

f1f9274bb9

Move VHDL global state management to a single file

The new state.cc/hh file now manages all the global
state that we maintain while generating VHDL. This
should make the code a bit tidier.

2009-01-17 09:19:58 -08:00

3 Commits