For functions without a port list in parantheses, declarations are optional in SystemVerilog.
This is true even in IEEE1800-2005, but not in IEEE1364-2005
(cherry picked from commit a4d91c9023)
__CYGWIN32__ is not defined when building with the 64-bit Cygwin
toolchain. According to the Cygwin FAQ, __CYGWIN__ has been defined
since 1998, so this should still work for users on 32-bit systems.
When module ports are collapsed, we can't tell which of the nexus drivers
are associated with a given module port and should be routed through an
associated modpath delay. Work round this by inserting a transparent
buffer or tran_vp if an output or inout port has a modpath delay. The
target code generator can elide this once it has handled the modpath
delays.
(cherry picked from commit e19109e58f)
These are assignments to a queue element, so need to consider the
element base type when determining the expression width.
(cherry picked from commit 8da7a14800)
Synthesis doesn't properly support any of the procedural continuous
assignment statements, so output a "sorry" message and abort synthesis.
(cherry picked from commit 387d18d222)
As for parentheses, we need to ignore commas within a pair of braces
when parsing a macro argument, e.g. `MACRO({a,b}) has one argument.
This fix is a little crude in that it doesn't distinguish between
parentheses and braces, e.g. it will accept {a,b). But any errors
like that will be caught by the compiler proper.
(cherry picked from commit fb29da0bd8)
See also: https://bugs.gentoo.org/706366
gcc-10 and above flipped a default from -fcommon to -fno-common:
https://gcc.gnu.org/PR85678
Usually all it takes is to add a few 'extern' declarations and
move definitions from header files to modules. I've port iverilog
to gcc-10 accroding to this guide:
https://wiki.gentoo.org/wiki/Gcc_10_porting_notes/fno_common
To fix this, I analyzed the code, and found ``pli_trace`` has been
defined at here:
https://github.com/steveicarus/iverilog/blob/v10_3/libveriuser/priv.c#L24
So I changed ``FILE* pli_trace;`` to ``extern FILE* pli_trace;``.
The var ``current_file`` only in ``cfparse_misc.h``, I changed it
from ``char *current_file;`` to ``extern char *current_file;`` and
declaring it in cflexor.lex
And then it works.
Signed-off-by: Huang Rui <vowstar@gmail.com>
(cherry picked from commit d49d26a5c5)
1364-2005 section 5.1.12 says "The right operand is always treated
as an unsigned number".
This fixes GitHub issue #283.
(cherry picked from commit 0a4cae2644)
If the condition expression is 2-state, the result won't be blended, so
the result will be a valid enum value if both true and false expressions
return the same enum type.
(cherry picked from commit 82c8a49573)
When strings are arguments to functions/tasks, that doesn't suddenly
make them implicitly scalar. Strings are vectors and should be treated
that was, even if they are IMPLICIT_REG.
Ported from git master.
Casting from signed to unsigned types and vice versa is legal in SV,
as is casting from a larger to a smaller size. Obey Verilog rules
for expression bit width and signedness.
(cherry picked from commit d56e90c3f4)
(modified to handle differences between devel and v10)
As reported on iverilog-devel on 2018-10-12, a dimension size of zero
could case the compiler to go into an infinite loop. Further tests
showed that unsized or queue dimensions entered as packed dimensions
would cause the compiler to crash.
(cherry picked from commit 832adc5c74)
This allows any always processes that are sensitive to the UDP output
to start first. This fixes a time 0 race that was found in a Lattice
Semiconductor simulation library (reported on iverilog-devel).
If the initial value is 'x', propagate the value to the UDP output
before the start of simulation, to avoid unwanted update events on
the z -> x transition on downstream nets.
(cherry picked from commit 3bdb50da29)
cfparse.h defines the YYLTYPE struct in case it has not been defined, and
also declares an extern YYLTYPE cflloc which is used in cflexor.
As cfparse_misc.h defines an extended YYLTYPE, the cflloc instance in
cfparse.c has this extended type, i.e. there is a type mismatch.
Changing the include order in cflexor causes both cflexor.c and
cfparse.c to use the definition from cfparse_misc.h.
This has been uncovered by GCC when using LTO:
---
gcc -flto=8 main.o substit.o cflexor.o cfparse.o -o iverilog
cfparse.h:105:16: warning: type of 'cflloc' does not match original declaration [-Wlto-type-mismatch]
105 | extern YYLTYPE cflloc;
| ^
cfparse.c:1162:9: note: type 'struct cfltype' should match type 'struct YYLTYPE'
1162 | YYLTYPE yylloc
| ^
cfparse.c:1162:9: note: 'cflloc' was previously declared here
cfparse.c:1162:9: note: code may be misoptimized unless '-fno-strict-aliasing' is used
---
(cherry picked from commit d58fde6f36)
In 64-bit Windows, an unsigned long is 32 bits, so initialising the num
member of the union did not properly initialise the ptr member. The num
member isn't actually needed, so eliminate it.
(cherry picked from commit c383d2048c)
- type is vpiPartSelect, not vpiMemoryWord
- left/right range is for part, not full word
- index is not valid for a part select
The user will now get a sensible error message if they pass part of an
array word to $dumpvars (GitHub issue #230).
(cherry picked from commit 8402696676)
If there are errors when parsing a file, it is not safe to elaborate any
modules that have been found in that file.
(cherry picked from commit 0cb1ebddf1)
Purdea Andrei
Cary R
Purdea Andrei
Martin Whitaker
Greg Steuck
Huang Rui
Stephen Williams
StefanBruens