6ba2bee977
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 20:40:30 +01:00
dc1c3a4043
Fix for GitHub issue #94 - enhance support for SystemVerilog size casting.
...
Allow the size expression to be any constant expression. Also ensure that
the expression width and type are correctly calculated and applied.
2016-03-25 21:49:28 +00:00
9538c81d34
Add check for explicit lifetime when initialising static variables.
...
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.
Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
2016-03-19 20:44:36 +00:00
6e718c2e0c
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 17:27:27 +00:00
635adfc01e
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 13:04:38 +00:00
9a7f31c728
Functions that return strings pass the return value on the stack.
2016-03-01 15:38:28 -08:00
e98bcb61bb
Fix for br988 - support begin/end blocks nested inside generate blocks.
...
This is syntax permitted in 1364-2001 but removed in 1364-2005.
Also update the iverilog man page to document the anachronisms warning
class that warns about use of this feature when a later generation is
selected.
2015-08-07 22:46:09 +01:00
853f119d83
Fix for br989 - unsupported attributes are not fatal.
...
The compiler was emitting a "sorry" message and aborting compilation when
it encountered attributes on a wire declaration/assignment. Change this
to a warning, as most attributes are ignored anyway.
2015-08-05 18:22:25 +01:00
311ffb27f2
ivl: Enum output ports are implicit regs when based on 'logic' type.
2015-06-24 23:53:33 +02:00
bdd0657140
Reject default task/function arguments when parsing traditional Verilog.
2015-06-21 09:05:39 +01:00
b23faff27c
Just a few more spelling fixes
...
Includes some user-visible messages
2015-06-17 08:09:34 -07:00
80403d2ade
ivl: Disabled reg_flag for time type in SV.
2015-06-08 18:42:52 +02:00
cd3180d1c2
ivl: TIME_LITERAL added as a primary expression.
2015-06-08 18:42:52 +02:00
71b1546a7d
Fail gracefully when an unpacked struct is declared.
2015-05-17 21:59:05 +01:00
352175d921
Fix for br973 - add support for enum declarations with no dimensions.
2015-04-26 12:46:08 +01:00
5dc1396eea
Spelling fixes
2015-04-13 11:35:12 -07:00
21c60b38e1
Fix space issues in the code.
2015-01-15 17:47:39 -08:00
b6e16aea6b
ivl: Typedefs may use unpacked arrays.
2015-01-12 11:08:31 +01:00
3f847fd927
Fix a compile warning
2015-01-10 16:28:55 -08:00
bca84d9dbb
Added parser support for SV modport declarations.
2015-01-10 11:10:41 +00:00
b400532169
Added support for interface declaration and instantiation.
...
modport and extern tf declarations are not yet supported.
2014-12-19 23:10:14 +00:00
6aa8e49b09
Add sorry message for unsupported arrays of named events.
2014-12-13 17:46:56 +00:00
daa59a95ad
ivl: Parsing rules for type casting.
2014-11-27 17:36:23 +01:00
cd992b4d5a
Add file/line information for parray data type.
2014-11-24 18:37:40 -08:00
c25538d750
Pass the integer type for enumerations to the IVL target stage
2014-10-31 18:09:19 -07:00
bfafd175fa
Fix parse.y bad handling of file names in some situations.
...
The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
2014-10-02 19:42:48 -07:00
d16a9dcfc6
Add support for calling a class function method using this/super
...
Also standardize the parser code that uses this/super.
2014-09-16 12:25:14 -07:00
acce9fc2a0
Report that external class methods/constructors are not supported
2014-09-11 16:35:24 -07:00
853512868b
Merge branch 'x-mil15'
2014-09-08 21:10:14 -07:00
9b1de4b038
Call IEEE 1800 SystemVerilog
2014-09-08 20:49:40 -07:00
ec2793c9b0
Warn that classes defined in the compilation unit scope are not supported
2014-09-08 16:59:18 -07:00
d1a35d5152
Handle nil queue as a was to delete a queue.
...
Treat this like assigning null to a dynamic array. This deletes the
queue and thus has the effect of clearing it.
2014-09-02 12:19:58 -07:00
f602ae84ab
Elaborate foreach loops as synthetic for loops.
...
Create an implicit scope to hold the index variable, and
generate a for loop to perform the functionality of the
foreach.
2014-08-21 16:44:46 -07:00
6d052d4ff7
Handle queue types and expressions at pform level.
2014-08-21 16:44:45 -07:00
2d2a720ea8
Do a better job with synthesis translate pragmas.
2014-08-09 08:04:25 -07:00
0cbd6d99af
SV: Add support for var decls in unnamed fork/join* blocks.
...
SystemVerilog allows variables to be declared in unnamed fork/join*
blocks. This patch adds support for this functionality.
2014-07-23 09:54:19 -07:00
8e7e3c7493
Remove space issue
2014-07-22 18:59:58 -07:00
588409389e
SV: Add support for var decls in unnamed begin/end blocks.
...
SystemVerilog allows variables to be declared in unnamed begin/end
blocks. This patch adds support for this functionality.
2014-07-22 18:58:23 -07:00
14f597acdd
Add support for synthesis translate meta-comments.
2014-07-15 18:03:40 -07:00
0611135758
Some more cppcheck cleanup/updates
2014-06-29 20:39:40 -07:00
734d56ce25
Remove space issue.
2014-04-10 14:37:07 -07:00
c8b20da4be
Merge pull request #21 from toddstrader/master
...
package imports in module headers
2014-04-07 14:09:50 -07:00
e55e832ea0
Handle unpacked arrays as output ports.
2014-04-06 08:40:09 -07:00
6caa41cc93
First pass at support for continuous assign of unpacked net arrays.
2014-04-06 08:40:09 -07:00
f8e33b12cd
Clean up pform_module_define_port in preparation for new tricks.
...
Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
2014-04-06 08:40:09 -07:00
aaee9989c2
Handle for_variable_declaration
...
This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
2014-04-06 08:40:08 -07:00
a849249a86
Allow typedefs to override inherited type names.
2014-04-06 08:40:08 -07:00
849ba64cf7
package imports in module headers
...
See IEEE 1800-2012 A.1.2 module_nonansi_header and module_ansi_header
2014-04-03 20:11:57 -04:00
a3450bf856
Fixes for GitHub issues 13 and 15.
...
The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').
I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
2014-02-25 20:39:21 +00:00
830083d99b
Merge branch 'x-sizer3'
2014-02-16 17:05:53 -08:00
Martin Whitaker
Stephen Williams
Maciej Suminski
Martin Whitaker
Larry Doolittle
Cary R
Todd Strader (todd.strader@gmail.com)