the PGAssign elaborate method used the test_width to get the width
of the r-value expression. This should be completely sufficient to
get the width of the expression, so always use a defined width to
elaborate the expression.
When ternary expressions are self-determined, use the test_width
method to get a proper reading of the expression width. Also improve
the test_width method to handle unsized operands.
The true and false expression clauses must have compatible types,
which are not necesarily identical. In particular, VT_BOOL and
VT_LOGIC are compatible for the purposes of ternary arguments. The
test in NetETernary::synthesize was incorrect.
In the process, fix the type handling of NetConst objects to allow
for IVL_VT_BOOL constants. This is information that the downstream
may find useful, so should be handled correctly.
Nothing to do with tab width! Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings. No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.
Low priority, simple entropy reduction. Please apply
unless it deletes some steganographic content you want
to keep.
In continuous assignment, the width of the expression needs to come
from the expression itself, and not just from the width of the l-value.
Use the PExpr::test_width method to get the width of the expression
to pass to the elaborate.
When the condition expression of a ternary is constant 1 or 0, we can
short-circuit the elaboration by only processing the clause (true or
false) that we need. This saves compile time and execution time.
It is possible for the left operand of a left shift to be not known
early during elaborate expression. In that case, make a punt expression
and expect it to be resolved later.
The expr:::synthesize methods need not deal with saturating left or
right shifts if they are dealt with early, in elaborate_expr methods.
So the elaborate_expr for shift takes on much more responsibility.
In signed contextx, the right shift and unary minus expressions need
to be sign extended before they operate, otherwise there may be bad
results in the high bits in the greater context.
The NetBranch object is connected, but not like an object, so the
NetPins object base class is factored out from NetObj to handle the
connectivity, and the NetBranch class uses the NetPins to connect a
branch.
Also, account for the fact that nets with a discipline are by default
real-valued.
Detect function call expressions that turn out to be calls to the
access function of a nature. Elaborate the access function and stub
the emit code. This gets the access function just short of the code
generator.
Contribution statements have an l-value and r-value. Parse those
expressions into pform so that elaboration has something to work with.
In this process, this patch also changes the PECallFunction class to
use the vector template instead of the svector template. The latter
doesn't add anything over the STL vector template, so this is a start
of working the svector out.
Part select of an entire signal returns just the NetESignal itself,
but since part selects are always unsigned, even if the selected
signal is signed, we need to cast the NetESignal to unsigned first.
The part select of a vector is converted by the compiler during
elaboration to a 0-based canonical address. But since it is legal
to address bits below the LSB, the canonical address can be negative.
So make the part select base for selecting from signals work with
signed arithmetic and make the code generator generate negative
indices when needed.
Part select of parameter names is fixed up to be structurally similar
to part select of signals, and also to behave similarly. (Though not
identically, for reason.)
Part selects to signals are allowed to be off the ends of the signal
itself. The bits that are beyond the vector return X. This may mean
creating constant X bits on one or both ends of the result.
A recent change to sb_to_idx() made it return a signed value
where it previously returned an unsigned value. This patch adds
explicit casts to remove the two signed vs unsigned comparison
warning messages.
Fix
elab_expr.cc:1561: warning: comparison between signed and unsigned integer expressions
caused by revised prototype of NetNet::sb_to_idx() in
commit dfb7bf5211
IEEE1364 has specific names for the various generations of Verilog that
are supported. Icarus Verilog should stick to those names for selection
the language feature set.
In the process, the extensions that were tied to the 2x generations
are pulled out out and given their own enable flags. The makes all the
feature control more regular and understandable.
Implement in behavioral the abs/min/max operators for real values.
The parser treats these builtin functions as operators, unary or
binary, and elaborates them appropriately.
Also add enough code generator support to handle real valued expressions
in thread context.
1364-2001 does not allow a replication count of zero, but
1364-2005 allows them when the replication is enclosed in
a concatenation with other valid bits. This patch adds
code to perform these checks for procedural expressions.
Because of the NetNet object must have a width greater
than zero a replication used in a continuous assignment
can never have a count of zero.
Logical and/or take as inputs condition expressions, which are scalar
expressions. Be sure to reduce vectors using proper logic to get the
right condition value.
When left-shifting unsized constants in self-determined contexts, the
constant value is normally pared down to its minimum required width.
But this practically guarantees loss of bits. Instead, detect this
special case and give the unsized constant a width of an integer.
Still allow for the super-special case that the shifted value and the
shift amount are constants. In that case, the result width (and value)
can be calculated precisely and there is no need to resort to default
widths.
Binary bit based operators were not padding arguments if they had
different widths. The reduction operators and ! were not correctly
evaluating their arguments in a self-determined context.
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.
These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
This patch adds a check and prints a warning message when the power
operator is used with unsigned bit based values. It also fixes a couple
of typos and adds an asserts if the above power operator happens to
get to the tgt-vvp back end.
Stephen Williams
Cary R
Larry Doolittle