225fcf6bf0
Pad CA bit arguments and make reductions and ! self-determined.
...
Binary bit based operators were not padding arguments if they had
different widths. The reduction operators and ! were not correctly
evaluating their arguments in a self-determined context.
2008-03-26 18:23:19 -07:00
fe72d02cf6
Major rework of the ternary operator elaboration code.
...
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.
These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
2008-03-08 19:45:13 -08:00
285ff2859f
Add power operator synthesize().
...
This patch adds synthesize() for the power operator.
2008-02-25 15:57:56 -08:00
fac1cc5a1c
Add user function synth and clean up expression code.
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This patch adds synthesize() for user functions. It also cleans up a
number of inconsistencies and missing checks in the expression code.
2008-02-24 20:00:18 -08:00
7975e14b5c
LineInfo uses perm_string for path.
...
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
2007-12-20 12:31:01 -05:00
fa2712a3ee
Fix for pr1851310.
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This patch fixes a bug in the compiler which prevented array words
from being correctly selected when used in the RHS of a continuous
assignment.
2007-12-15 15:56:54 -08:00
083b9b6ee6
Handle repeat concatenation in continuous assign
...
When a repeat concatenation expression is translated to a netlist,
get the repeat expression right. This comes up when an elab_and_eval
elaboration contains a repeat concationation, and the expression is
ultimately turned into a netlist by expr_synth.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-01 17:36:57 -07:00
c7d97f4146
Properly evaluate scope path expressions.
2007-06-02 03:42:12 +00:00
8ed1a010f7
Allow bit/part select of vectors in continuous assignments.
2007-04-15 01:37:29 +00:00
2229825783
fix handling of unary reduction logic in certain nets.
2007-04-12 05:21:54 +00:00
a863b2390c
Remove useless assert
2007-04-04 02:31:57 +00:00
326329d497
Set some missing local flags.
2007-02-05 01:42:31 +00:00
4b829bf04f
Get argument widths right for shift results.
2007-01-20 02:10:45 +00:00
91d84e7dc7
Major rework of array handling. Memories are replaced with the
...
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
2007-01-16 05:44:14 +00:00
fc0695beb6
Handle 64bit delay constants.
2006-08-08 05:11:37 +00:00
49b65e86fe
Add support for power in constant expressions.
2006-07-31 03:50:17 +00:00
ed70db84ce
Handle real valued literals in net contexts.
2006-07-08 21:48:46 +00:00
a8b86ea3bb
More explicit datatype setup.
2006-05-01 20:47:58 +00:00
dc2898cc73
fix net type of multiply output.
2006-05-01 05:40:21 +00:00
0c9fb766b6
Get the data type of part select results right.
2006-04-30 05:17:48 +00:00
a4116efd57
Fix the return type of a synthesized divide.
2006-01-03 05:15:33 +00:00
7235706923
Make sure div, mod and mult nodes have line number info.
2005-09-15 23:04:09 +00:00
b69f59f2ec
Handle memory references is continuous assignments.
2005-08-31 05:07:31 +00:00
73f3589ea6
use NetPartSelect to shrink part from high bits.
2005-06-13 23:22:14 +00:00
9278dad244
Make synthesized padding vector-aware.
2005-06-13 22:26:03 +00:00
3bd09d1470
synthesis of Logic and shifts using vector gates.
2005-05-15 04:47:00 +00:00
d548c9a5f8
Handle synthesis of concatenation expressions.
2005-05-06 00:25:13 +00:00
af7e196518
synthesis of add and unary get vector widths right.
2005-04-25 01:30:31 +00:00
365cfedd55
Update DFF support to new data flow.
2005-04-24 23:44:01 +00:00
ab1ca54df2
Update support for LPM_MOD.
2005-03-12 06:43:35 +00:00
257e1f9516
Support shifts and divide.
2005-02-19 02:43:38 +00:00
d74177634c
Restructure NetMux devices to pass vectors.
...
Generate NetMux devices from ternary expressions,
Reduce NetMux devices to bufif when appropriate.
2005-02-12 06:25:40 +00:00
99ace10774
Simplified NetMult and IVL_LPM_MULT.
2005-01-28 05:39:33 +00:00
bf6a5d0f50
Implement LPM_COMPARE nodes as two-input vector functors.
2005-01-16 04:20:32 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
...
of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
3dbc07f34d
Implement signed divide and signed right shift in nets.
2004-06-30 02:16:26 +00:00
2d63705093
Connect rsif of multiply to DataB.
2004-06-16 16:21:34 +00:00
e8e0cd7cab
Support / and % in synthesized contexts.
2004-06-12 15:00:02 +00:00
ba309e60bb
Fix synthesis method for logical and/or
2004-06-01 01:04:57 +00:00
177b6ffb6a
Addtrbute keys are perm_strings.
2004-02-20 18:53:33 +00:00
27af95d402
Use perm_strings for named langiage items.
2004-02-18 17:11:54 +00:00
2f8a40b159
Fix evaluation of compare to constant expression.
2004-02-15 04:23:48 +00:00
8eccb7b9a1
Remove redundant scope tokens.
2003-11-10 19:39:20 +00:00
4eae8426a9
More flexible width handling for synthesized add.
2003-10-27 06:04:21 +00:00
1cb589fee0
Assure ternary arguments are wide enough.
2003-09-26 02:44:27 +00:00
b0230cf4d4
Support synthesis of constant downshifts.
2003-09-03 23:31:36 +00:00
7c1401a2ba
Spelling patch.
2003-08-28 04:11:17 +00:00
a95463ff81
Add support for IVL_LPM_MULT device.
2003-08-09 03:23:03 +00:00
bfe31e22bf
Start handling pad of expressions in code generators.
2003-07-26 03:34:42 +00:00
21ff80075a
Various warnings fixed.
2003-06-24 01:38:02 +00:00
Cary R
Stephen Williams
Martin Whitaker
steve