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14 Commits

Author SHA1 Message Date
Andrew Pullin d540260a20 Fix #1170: Skip $unit scope in tgt-sizer 
The tgt-sizer target now skips IVL_SCT_PACKAGE scopes (the SystemVerilog
$unit compilation unit scope) instead of erroring. This allows sizer to
work with -g2012 and other SystemVerilog modes.

Includes regression test: br_gh1170

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-01-24 16:47:11 -08:00
Cary R 78fa7a5a10 Update program copyright to 2026 2026-01-13 02:04:37 -08:00
Cary R 94dcd658c8 Update exe and manual pages to report @(C) 2025 2025-10-12 19:13:30 -07:00
Cary R fcb543d6e5 Some cppcheck cleanup 2025-10-12 17:37:50 -07:00
Cary R dc047799d6 Update displayed Copyright 2024-01-20 17:52:04 -08:00
Cary R ee14cb0eb0 Update displayed Copyright dates 2023-06-10 20:33:08 -07:00
Cary R fb237fb006 Update the user visible copyright to be 2020 2020-05-31 13:41:38 -07:00
Cary R 0ffd61a835 Remove some cppcheck warnings 2014-06-28 16:56:09 -07:00
Stephen Williams f8dc430fe5 Add synthesis support for casez statements. 
This generates an EQZ LPM device that carries the case-z-ness to
the code generator.

Also add to the vvp code generator support for the EQZ device so
that the synthesis results can be simulated.

Account for the wildcard devices in the sizer.
 2014-06-13 18:01:41 -07:00
Stephen Williams 579b59b8eb Sizer recognizes more LPM types. 2014-05-25 19:38:12 -07:00
Stephen Williams 463407572f Sizer pay attention to ivl_synthesis_off attribute. 2014-02-15 14:44:55 -08:00
Stephen Williams 9f2b7d6553 Rearrange counters to me more realistic 
Instead of counting gate types, convert to gate count estimates
and some other interesting statistics. Also handling the descent
into child scopes.
 2014-02-09 08:59:51 -08:00
Stephen Williams f5041e6c09 Collect some actual sizer statistics. 2014-02-08 18:53:42 -08:00
Stephen Williams 959ac3229e Start a sizer backend. 2014-02-08 10:16:11 -08:00