Report every source position as the compact string "start:begin:end" of
byte offsets (begin/end empty when not applicable): a port/signal is
"start::", a module "start::end" (module .. endmodule), an instance
"start::end" (.. ';'), and an always/initial block or generate frame
"start:begin:end". This replaces the {"off":0,"line":N,"col":0} object
whose off/col were always zero, and matches the GHDL --flow exporter's
format so one consumer works across both tools.
The ivl_target API exposes only line numbers, so the byte offsets and
begin/end spans are recovered by a small comment/string-aware scanner
that reads the source files (cached, with a per-file line table).
Bump the schema to flowtracer1.verilog.v0 (companion to GHDL's
flowtracer1.vhdl.v0). flow_reg.py checks the new schema and that every
pos/inst_pos is well formed; tgt-flow.rst documents the position format.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Add a new compile-time code-generator target that exports the elaborated
design as a JSON dataflow database (schema flowtracer1.merged.v0), shared
with the GHDL --flow exporter so a single consumer works across Verilog
and VHDL designs.
The exporter walks the elaborated netlist via ivl_target.h and emits:
- modules[] keyed by module type, with ports/generics/signals and
name-based processes[] and assignments[] (reads/drives/sensitivity
as signal names);
- hierarchy[] with port_map associations resolved through the shared
nexus, and generate blocks as transparent scope:true frames;
- a secondary integer-id nets[]/cells[] graph (drivers/loads,
clocked/clock_net).
Process reads/drives come from walking the statement/expression tree;
continuous assigns are recovered from logic/LPM devices with transitive
backward-cone resolution through synthetic nets. Generate scopes are
transparent to dataflow attribution and to port-map actual resolution.
Wired into the build (SUBDIRS, configure.ac), documented in
Documentation/targets/tgt-flow.rst, and covered by ivtest/flow_reg.py
(flow_basic, flow_comb, flow_generate, flow_genpath).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Embed the Icarus Verilog documentation, and format it so that the
Sphinx tools can process it into html or other formats. This will
make the documentation easier to keep up to date with the actual
software.
William P. Moore
Cary R
mole99
Emilio Miralles
Stephen Williams