Currently the vvp target emits unary real minus as `0.0 - value`.
This is not the same operation for all real values. It loses the
negative zero result for `-(+0.0)` and does not reliably flip the sign
bit for NaN values whose bits are visible through `$realtobits`.
Add `%neg/wr` and use it for unary real minus. This performs a direct
negation of the real stack value, so zero, NaN and infinity all use the
same operation as unary minus instead of a binary subtraction from zero.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Report every source position as the compact string "start:begin:end" of
byte offsets (begin/end empty when not applicable): a port/signal is
"start::", a module "start::end" (module .. endmodule), an instance
"start::end" (.. ';'), and an always/initial block or generate frame
"start:begin:end". This replaces the {"off":0,"line":N,"col":0} object
whose off/col were always zero, and matches the GHDL --flow exporter's
format so one consumer works across both tools.
The ivl_target API exposes only line numbers, so the byte offsets and
begin/end spans are recovered by a small comment/string-aware scanner
that reads the source files (cached, with a per-file line table).
Bump the schema to flowtracer1.verilog.v0 (companion to GHDL's
flowtracer1.vhdl.v0). flow_reg.py checks the new schema and that every
pos/inst_pos is well formed; tgt-flow.rst documents the position format.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Add a new compile-time code-generator target that exports the elaborated
design as a JSON dataflow database (schema flowtracer1.merged.v0), shared
with the GHDL --flow exporter so a single consumer works across Verilog
and VHDL designs.
The exporter walks the elaborated netlist via ivl_target.h and emits:
- modules[] keyed by module type, with ports/generics/signals and
name-based processes[] and assignments[] (reads/drives/sensitivity
as signal names);
- hierarchy[] with port_map associations resolved through the shared
nexus, and generate blocks as transparent scope:true frames;
- a secondary integer-id nets[]/cells[] graph (drivers/loads,
clocked/clock_net).
Process reads/drives come from walking the statement/expression tree;
continuous assigns are recovered from logic/LPM devices with transitive
backward-cone resolution through synthetic nets. Generate scopes are
transparent to dataflow attribution and to port-map actual resolution.
Wired into the build (SUBDIRS, configure.ac), documented in
Documentation/targets/tgt-flow.rst, and covered by ivtest/flow_reg.py
(flow_basic, flow_comb, flow_generate, flow_genpath).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Add flags to enable IEEE1800-2017 and IEEE1800-2023 languages generations
and also support them in the `begin_keywords macro. Since neither defines
new keywords they'll use the same keyword mask as 2012.
Update the driver, compiler, documentation and regression test harness so
-g2017 and -g2023 are recognized as language generation flags.
There are no specific features from these versions added yet, this is just
the necessary infrastructure to allow gating new features from those
generations when they are added later.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- change documentation theme from `alabaster` to `shibuya`
- add pinned Documentation requirements for `sphinx` and `shibuya`
- update workflows to create `.venv` and install with `requirements.txt`
- ignore common virtual environment directories (`.conda` and `.venv`)
The new option allows parameter, net and events to be used before
declaration. With variants
-gno-strict-net-declaration for nets and events,
-gno-strict-parameter-declaration for parameters.
With `-ggno-strict-parameter-declaration` a warning is issued for
parameter use before declaration. This warning suppressed with
the new class `-Wno-declaration-after-use`, instead of `-Wno-anachronisms`.
The standards requires that parameters must be declared
before they are used. Using -gno-strict-parameter-declaration
will allow using a parameter before declaration, e.g., in a port
declaration, with the parameter declared in the body of the
module. Prior to version 13 this was allowed, so there is a large body
of existing code depending on the pre version 13 behaviour.
Although the introductory paragraph seems clear enough, add a reminder
at the start of the section on extended arguments that they must appear
after the input file name.
This removes the regress-msys2.list file, fixes the output from the
pr2509349a.v test to not be different on different systems, and
documents the $readmempath task.
wm2015email
Lars-Peter Clausen
Haowei Hsu
Ralf Habacker
Martin Whitaker
Stephan I. Böttcher
Stephan I. Böttcher
Cary R.
أحمد المحمودي (Ahmed El-Mahmoudy)
Oscar Gustafsson
henry
ga
Stephen Williams
Ethan Sifferman