Merge 8428032d83 into 31d1850bc8
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4f8323f27c
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@ -21,3 +21,4 @@ Icarus Verilog. The code generator is selected by the "-t" command line flag.
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tgt-sizer
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tgt-verilog
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tgt-blif
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tgt-flow
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@ -0,0 +1,99 @@
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The Flow Dataflow Exporter (-tflow)
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===================================
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The flow code generator exports the elaborated design as a JSON
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*dataflow database* rather than a simulation or netlist artifact. The
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output describes the module hierarchy, the ports/parameters/signals of
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each module, and the dataflow graph (which processes and continuous
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assignments read and drive which nets), so that IDEs and analysis tools
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can render dataflow panels, browse the elaborated hierarchy, and trace
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input-to-output continuity across the design.
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The emitted schema (``flowtracer1.verilog.v0``) is the Verilog companion
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to the GHDL ``--flow`` exporter (``flowtracer1.vhdl.v0``), so a single
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consumer works across Verilog (via this target) and VHDL (via GHDL)
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designs.
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USAGE
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-----
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::
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% iverilog -tflow -o<path>.flow <source files>...
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The flow target runs at elaboration time; no simulation is performed.
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The root module of the elaborated design becomes the ``top`` of the
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exported database. Because the exporter reads the fully elaborated
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netlist, parameter values, generate blocks, and instance bindings are
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all resolved.
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OUTPUT
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------
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The output is a single JSON object with these top-level fields:
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``schema``
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Always ``"flowtracer1.verilog.v0"``.
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``top``
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The basename of the root module instance.
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``modules``
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One entry per module *type*, each with ``ports`` (name/direction/
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type), ``generics`` (parameters), ``signals``, the name-based
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``processes`` and ``assignments`` (with ``reads``/``drives``/
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``sensitivity`` given as signal names), and the ``instances`` it
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contains (with ``port_map`` and resolved ``generic_map``).
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``hierarchy``
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The elaborated instance tree. Each node carries its ``port_map``
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(formal-to-actual associations resolved through the shared net) and
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``children``. Generate blocks appear as transparent frames marked
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``"scope": true`` with a ``generate`` object describing the kind
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(``for``/``if``), label, and index.
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``nets`` and ``cells``
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A secondary, integer-id dataflow graph: ``nets`` are the canonical
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nexuses (with ``drivers``/``loads`` referring to cell ids) and
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``cells`` are the processes, gates, LPM devices, and constants (with
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``drives``/``reads`` referring to net ids, plus ``clocked`` and
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``clock_net``).
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POSITIONS
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---------
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Every ``pos`` / ``inst_pos`` is a compact string of byte offsets,
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``"start:begin:end"``, to help source-scanning consumers (such as Perl
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lexers) locate constructs:
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* *start* -- byte offset of the construct (first non-blank character of
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its line);
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* *begin* -- byte offset of the ``begin`` keyword that opens a
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procedural or generate block -- empty when there is none;
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* *end* -- byte offset of the closing ``end``/``endmodule`` keyword or
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the terminating ``;`` -- empty for a plain point.
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So a port or signal is ``"start::"``, a module is ``"start::end"``
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(``module`` .. ``endmodule``), an instance is ``"start::end"`` (.. ``;``),
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and an ``always``/``initial`` block or generate frame is
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``"start:begin:end"``. Because the ``ivl_target`` API exposes only line
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numbers, the exporter reads the source files and scans them (comment- and
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string-aware) to recover these byte offsets and spans.
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LIMITATIONS
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-----------
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Continuity through bit- and part-selects (for example a generate that
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connects ``.d(bus[i])``) is not yet represented at the individual-bit
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level; whole-signal connections are tracked.
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For a process sensitive to several edges (for example an
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asynchronous-reset flip-flop ``@(posedge clk or posedge rst)``), the
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``clock_net`` field reports the first edge signal.
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Constant tie-offs and synthetic compiler temporaries are summarized
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rather than reported individually.
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@ -40,7 +40,7 @@ VERSION_MAJOR = @VERSION_MAJOR@
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VERSION_MINOR = @VERSION_MINOR@
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SUBDIRS = ivlpp vhdlpp vvp vpi tgt-null tgt-stub tgt-vvp \
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tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif tgt-sizer driver \
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tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif tgt-sizer tgt-flow driver \
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ivtest
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# Only run distclean for these directories.
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NOTUSED = tgt-fpga tgt-pal tgt-verilog
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@ -453,6 +453,7 @@ AC_CONFIG_FILES([
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ivtest/Makefile
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libveriuser/Makefile
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tgt-blif/Makefile
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tgt-flow/Makefile
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tgt-fpga/Makefile
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tgt-null/Makefile
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tgt-pal/Makefile
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@ -0,0 +1,11 @@
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# Test list for the flow (-tflow) dataflow exporter target.
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#
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# Each entry names a Verilog source under flow/<name>.v. The runner
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# flow_reg.py compiles it with `iverilog -tflow`, parses the resulting
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# .flow JSON, and checks structural expectations (schema, hierarchy,
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# processes/assignments, generate frames). Run with: python3 flow_reg.py
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#
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flow_basic
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flow_comb
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flow_generate
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flow_genpath
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@ -0,0 +1,3 @@
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*.flow
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*.log
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log/
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@ -0,0 +1,30 @@
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// Phase 0 test design: a counter instantiated inside a top module,
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// to exercise scope hierarchy + nexus reachability in tgt-flow.
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module counter #(parameter WIDTH = 4) (
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input wire clk,
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input wire rst,
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input wire en,
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output reg [WIDTH-1:0] count
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);
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always @(posedge clk or posedge rst) begin
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if (rst)
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count <= {WIDTH{1'b0}};
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else if (en)
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count <= count + 1'b1;
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end
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endmodule
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module top (
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input wire clk,
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input wire rst,
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output wire [3:0] q
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);
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wire enable = 1'b1;
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counter #(.WIDTH(4)) u_cnt (
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.clk (clk),
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.rst (rst),
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.en (enable),
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.count (q)
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);
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endmodule
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@ -0,0 +1,47 @@
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// Richer Phase 2 test: comb always with case, ternary, continuous
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// assign, and two levels of hierarchy.
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module alu (
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input wire [1:0] op,
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input wire [7:0] a,
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input wire [7:0] b,
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output reg [7:0] y
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);
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always @(*) begin
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case (op)
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2'b00: y = a + b;
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2'b01: y = a - b;
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2'b10: y = a & b;
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default: y = a ^ b;
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endcase
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end
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endmodule
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module datapath (
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input wire [1:0] sel,
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input wire [7:0] x,
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input wire [7:0] z,
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output wire [7:0] result,
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output wire is_zero
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);
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wire [7:0] alu_out;
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alu u_alu (.op(sel), .a(x), .b(z), .y(alu_out));
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assign result = alu_out;
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assign is_zero = (alu_out == 8'b0) ? 1'b1 : 1'b0;
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endmodule
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module chip (
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input wire [1:0] mode,
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input wire [7:0] in0,
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input wire [7:0] in1,
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output wire [7:0] out,
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output wire zero
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);
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datapath u_dp (
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.sel (mode),
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.x (in0),
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.z (in1),
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.result (out),
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.is_zero(zero)
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);
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endmodule
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@ -0,0 +1,28 @@
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// Phase 3 test: for-generate replicating a sub-module, plus an
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// if-generate, to exercise generate-frame emission.
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module inv #(parameter ID = 0) (
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input wire d,
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output wire q
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);
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assign q = ~d;
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endmodule
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module gen_top #(parameter N = 3) (
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input wire [2:0] din,
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output wire [2:0] dout
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);
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genvar i;
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generate
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for (i = 0; i < 3; i = i + 1) begin : row
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inv #(.ID(i)) u_cell (.d(din[i]), .q(dout[i]));
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end
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endgenerate
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generate
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if (N > 0) begin : opt
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wire tap;
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assign tap = din[0];
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end
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endgenerate
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endmodule
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@ -0,0 +1,13 @@
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// Generate frame with WHOLE-signal port connections (isolates frame
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// transparency from bit-select handling).
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module inv8 (input wire [7:0] d, output wire [7:0] q);
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assign q = ~d;
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endmodule
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module wrap (input wire [7:0] din, output wire [7:0] dout);
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generate
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if (1) begin : blk
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inv8 u_inv (.d(din), .q(dout));
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end
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endgenerate
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endmodule
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@ -0,0 +1,210 @@
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''' Regression runner for the flow (-tflow) dataflow exporter target.
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For each test named in flow.list, this compiles flow/<name>.v with
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`iverilog -tflow` and validates the resulting flowtracer1.verilog.v0
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JSON: every output must be well-formed and carry the expected schema,
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a top, and a non-empty module/hierarchy set; per-test checks then
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assert the dataflow facts the exporter is meant to capture (clocked
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processes, port-map continuity, continuous-assign cone reads, and
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generate frames).
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Run with: python3 flow_reg.py '''
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import os
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import re
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import json
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import subprocess
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# Name of the iverilog command. May vary in different installations.
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IVERILOG = "iverilog"
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def get_tests() -> list:
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'''Read the test names from flow.list (first word of each line).'''
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match_prog = re.compile(r"^([a-zA-Z0-9_.]+).*$")
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tests = []
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with open("flow.list", encoding='ascii') as fd:
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for line in fd:
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if line[0] == "#":
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continue
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match = match_prog.search(line)
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if match:
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tests.append(match.group(1))
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return tests
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# ---- per-test structural checks ----------------------------------------
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# Each returns (ok, message). `d` is the parsed .flow document.
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def _module(d, name):
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for m in d["modules"]:
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if m["name"] == name:
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return m
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return None
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def _find_in_hier(d, pred):
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'''Depth-first search of hierarchy[] for a node matching pred.'''
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stack = list(d["hierarchy"])
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while stack:
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n = stack.pop()
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if pred(n):
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return n
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stack.extend(n.get("children", []))
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return None
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def check_basic(d):
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if d["top"] != "top":
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return False, "top != 'top'"
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cnt = _module(d, "counter")
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if not cnt:
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return False, "no 'counter' module"
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proc = [p for p in cnt["processes"]
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if "count" in p["drives"] and p.get("sensitivity")]
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if not proc:
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return False, "no clocked process driving count"
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# port_map continuity: u_cnt.count maps to parent net q
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node = _find_in_hier(d, lambda n: n.get("module") == "counter")
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if not node:
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return False, "counter instance not in hierarchy"
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pm = {a["formal"]: a["actuals"] for a in node["port_map"]}
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if "q" not in pm.get("count", []):
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return False, "port_map count->q missing"
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return True, "clocked process + port_map ok"
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def check_comb(d):
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if d["top"] != "chip":
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return False, "top != 'chip'"
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dp = _module(d, "datapath")
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if not dp:
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return False, "no 'datapath' module"
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res = [a for a in dp["assignments"]
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if a["target"] == "result" and "alu_out" in a["reads"]]
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if not res:
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return False, "assign result<-alu_out (cone) missing"
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return True, "continuous-assign cone read ok"
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|
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def check_generate(d):
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frame = _find_in_hier(d, lambda n: n.get("scope") is True
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and "generate" in n)
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if not frame:
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return False, "no generate frame in hierarchy"
|
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kind = frame["generate"].get("kind")
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if kind not in ("for", "if"):
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return False, "generate.kind not for/if"
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return True, "generate frame ({}) ok".format(kind)
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||||
|
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|
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def check_genpath(d):
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# if-generate with whole-signal connection: the instance under the
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# frame must resolve its actuals to the parent nets.
|
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inst = _find_in_hier(d, lambda n: n.get("module") == "inv8")
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||||
if not inst:
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return False, "inv8 instance not found under frame"
|
||||
pm = {a["formal"]: a["actuals"] for a in inst["port_map"]}
|
||||
if "din" not in pm.get("d", []) or "dout" not in pm.get("q", []):
|
||||
return False, "port_map through frame not resolved"
|
||||
return True, "generate-frame port_map ok"
|
||||
|
||||
|
||||
CHECKS = {
|
||||
"flow_basic": check_basic,
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"flow_comb": check_comb,
|
||||
"flow_generate": check_generate,
|
||||
"flow_genpath": check_genpath,
|
||||
}
|
||||
|
||||
|
||||
def run_test(test_name: str) -> bool:
|
||||
'''Compile one test with -tflow and validate its JSON.'''
|
||||
src = "flow/" + test_name + ".v"
|
||||
out = "flow/" + test_name + ".flow"
|
||||
|
||||
cmd = IVERILOG + " -g2012 -tflow -o" + out + " " + src
|
||||
rc = subprocess.call(cmd + " > log/" + test_name + ".log 2>&1", shell=True)
|
||||
if rc != 0:
|
||||
return False
|
||||
|
||||
try:
|
||||
with open(out, encoding='ascii') as fd:
|
||||
doc = json.load(fd)
|
||||
except (OSError, ValueError):
|
||||
return False
|
||||
|
||||
# Invariants common to every well-formed output.
|
||||
if doc.get("schema") != "flowtracer1.verilog.v0":
|
||||
return False
|
||||
if not doc.get("top") or not doc.get("modules") or not doc.get("hierarchy"):
|
||||
return False
|
||||
# Every position is the compact "start:begin:end" byte-offset string.
|
||||
if not _positions_well_formed(doc):
|
||||
return False
|
||||
|
||||
check = CHECKS.get(test_name)
|
||||
if check:
|
||||
ok, _msg = check(doc)
|
||||
return ok
|
||||
return True
|
||||
|
||||
|
||||
_POS_RE = re.compile(r"^[0-9]*:[0-9]*:[0-9]*$")
|
||||
|
||||
|
||||
def _positions_well_formed(node) -> bool:
|
||||
'''Every "pos"/"inst_pos" value, anywhere in the document, must be the
|
||||
compact "start:begin:end" byte-offset string (parts may be empty).'''
|
||||
if isinstance(node, dict):
|
||||
for key, val in node.items():
|
||||
if key in ("pos", "inst_pos"):
|
||||
if not (isinstance(val, str) and _POS_RE.match(val)):
|
||||
return False
|
||||
elif not _positions_well_formed(val):
|
||||
return False
|
||||
return True
|
||||
if isinstance(node, list):
|
||||
return all(_positions_well_formed(x) for x in node)
|
||||
return True
|
||||
|
||||
|
||||
def get_ivl_version() -> list:
|
||||
'''Get the iverilog version.'''
|
||||
text = subprocess.check_output([IVERILOG, "-V"])
|
||||
match = re.search(b'Icarus Verilog version ([0-9]+)\\.([0-9]+)', text)
|
||||
if not match:
|
||||
return None
|
||||
items = match.groups()
|
||||
return [str(items[0], 'ascii'), str(items[1], 'ascii')]
|
||||
|
||||
|
||||
def run_tests(tests: list):
|
||||
'''Run all tests in the list.'''
|
||||
ivl_ver = get_ivl_version()
|
||||
print("Running flow tests for Icarus Verilog version: {}.{}".format(
|
||||
ivl_ver[0], ivl_ver[1]))
|
||||
print("=" * 50)
|
||||
|
||||
if not os.path.exists("log"):
|
||||
os.mkdir("log")
|
||||
|
||||
count_passed = 0
|
||||
count_failed = 0
|
||||
width = max(len(name) for name in tests)
|
||||
for test in tests:
|
||||
passed = run_test(test)
|
||||
if passed:
|
||||
count_passed += 1
|
||||
res = "Passed"
|
||||
else:
|
||||
count_failed += 1
|
||||
res = "Failed"
|
||||
print("{name:>{width}}: {res}.".format(name=test, width=width, res=res))
|
||||
|
||||
print("=" * 50)
|
||||
print("Tests results: Passed {}, Failed {}".format(count_passed, count_failed))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
run_tests(get_tests())
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
#
|
||||
# This source code is free software; you can redistribute it
|
||||
# and/or modify it in source code form under the terms of the GNU
|
||||
# Library General Public License as published by the Free Software
|
||||
# Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU Library General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU Library General Public
|
||||
# License along with this program; if not, write to the Free
|
||||
# Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
SHELL = /bin/sh
|
||||
|
||||
suffix = @install_suffix@
|
||||
|
||||
prefix = @prefix@
|
||||
exec_prefix = @exec_prefix@
|
||||
srcdir = @srcdir@
|
||||
|
||||
VPATH = $(srcdir)
|
||||
|
||||
bindir = @bindir@
|
||||
libdir = @libdir@
|
||||
includedir = $(prefix)/include
|
||||
|
||||
CC = @CC@
|
||||
INSTALL = @INSTALL@
|
||||
INSTALL_PROGRAM = @INSTALL_PROGRAM@
|
||||
INSTALL_DATA = @INSTALL_DATA@
|
||||
|
||||
ifeq (@srcdir@,.)
|
||||
INCLUDE_PATH = -I. -I..
|
||||
else
|
||||
INCLUDE_PATH = -I. -I.. -I$(srcdir) -I$(srcdir)/..
|
||||
endif
|
||||
|
||||
CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@ @PICFLAG@
|
||||
CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
|
||||
LDFLAGS = @LDFLAGS@
|
||||
|
||||
O = flow.o
|
||||
|
||||
all: dep flow.tgt
|
||||
|
||||
check: all
|
||||
|
||||
clean:
|
||||
rm -rf *.o dep flow.tgt
|
||||
|
||||
distclean: clean
|
||||
rm -f Makefile config.log
|
||||
|
||||
cppcheck: $(O:.o=.c)
|
||||
cppcheck --enable=all --std=c99 --std=c++11 -f \
|
||||
--check-level=exhaustive \
|
||||
--suppressions-list=$(srcdir)/../cppcheck-global.sup \
|
||||
--relative-paths=$(srcdir) $(INCLUDE_PATH) $^
|
||||
|
||||
Makefile: $(srcdir)/Makefile.in ../config.status
|
||||
cd ..; ./config.status --file=tgt-flow/$@
|
||||
|
||||
dep:
|
||||
mkdir dep
|
||||
|
||||
%.o: %.c | dep
|
||||
$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
|
||||
mv $*.d dep
|
||||
|
||||
ifeq (@WIN32@,yes)
|
||||
TGTLDFLAGS=-L.. -livl
|
||||
TGTDEPLIBS=../libivl.a
|
||||
else
|
||||
TGTLDFLAGS=
|
||||
TGTDEPLIBS=
|
||||
endif
|
||||
|
||||
flow.tgt: $O $(TGTDEPLIBS)
|
||||
$(CC) @shared@ $(LDFLAGS) -o $@ $O $(TGTLDFLAGS)
|
||||
|
||||
install: all installdirs installfiles
|
||||
|
||||
F = ./flow.tgt \
|
||||
$(srcdir)/flow.conf \
|
||||
$(srcdir)/flow-s.conf
|
||||
|
||||
installfiles: $(F) | installdirs
|
||||
$(INSTALL_PROGRAM) ./flow.tgt "$(DESTDIR)$(libdir)/ivl$(suffix)/flow.tgt"
|
||||
$(INSTALL_DATA) $(srcdir)/flow.conf "$(DESTDIR)$(libdir)/ivl$(suffix)/flow.conf"
|
||||
$(INSTALL_DATA) $(srcdir)/flow-s.conf "$(DESTDIR)$(libdir)/ivl$(suffix)/flow-s.conf"
|
||||
|
||||
installdirs: $(srcdir)/../mkinstalldirs
|
||||
$(srcdir)/../mkinstalldirs "$(DESTDIR)$(libdir)/ivl$(suffix)"
|
||||
|
||||
uninstall:
|
||||
rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/flow.tgt"
|
||||
rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/flow.conf"
|
||||
rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/flow-s.conf"
|
||||
|
||||
|
||||
-include $(patsubst %.o, dep/%.d, $O)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
functor:synth2
|
||||
functor:synth
|
||||
functor:syn-rules
|
||||
functor:cprop
|
||||
functor:nodangle
|
||||
flag:DLL=flow.tgt
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
functor:cprop
|
||||
functor:nodangle
|
||||
flag:DLL=flow.tgt
|
||||
Loading…
Reference in New Issue