b90cda1f3f
Carry strength values from Verilog source to the
...
pform and netlist for gates.
Change vvm constants to use the driver_t to drive
a constant value. This works better if there are
multiple drivers on a signal.
2000-05-07 04:37:55 +00:00
fbe475ef7d
Add infrastructure for system functions, move
...
$time to that structure and add $random.
2000-05-04 03:37:58 +00:00
69612ceb73
Move memories to the NetScope object.
2000-05-02 03:13:30 +00:00
8d8f1e2401
Move signal tables to the NetScope class.
2000-05-02 00:58:11 +00:00
acfb5c177d
Over agressive signal elimination in constant probadation.
2000-04-28 21:00:28 +00:00
a8114ae122
Add support for the procedural release statement.
2000-04-23 03:45:24 +00:00
44838f8973
Add support for force assignment.
2000-04-22 04:20:19 +00:00
4493e968da
Finally remove the NetNEvent and NetPEvent classes,
...
Get synthesis working with the NetEvWait class,
and get started supporting multiple events in a
wait in vvm.
2000-04-12 20:02:52 +00:00
b1fd927acb
Named events really should be expressed with PEIdent
...
objects in the pform,
Handle named events within the mix of net events
and edges. As a unified lot they get caught together.
wait statements are broken into more complex statements
that include a conditional.
Do not generate NetPEvent or NetNEvent objects in
elaboration. NetEvent, NetEvWait and NetEvProbe
take over those functions in the netlist.
2000-04-12 04:23:57 +00:00
8dbd64121f
All events now use the NetEvent class.
2000-04-10 05:26:05 +00:00
30e8289239
Simulate named event trigger and waits.
2000-04-04 03:20:15 +00:00
b62a7ace5c
Remove the useless sref template.
2000-04-02 04:26:06 +00:00
694ff934af
Add support for integer division.
2000-04-01 21:40:22 +00:00
d97ab9be23
New and improved combinational primitives.
2000-03-29 04:37:10 +00:00
6eef54595f
Support localparam.
2000-03-12 17:09:40 +00:00
e7efc2709a
Redesign the implementation of scopes and parameters.
...
I now generate the scopes and notice the parameters
in a separate pass over the pform. Once the scopes
are generated, I can process overrides and evalutate
paremeters before elaboration begins.
2000-03-08 04:36:53 +00:00
b734ecf02f
Macintosh compilers do not support ident.
2000-02-23 02:56:53 +00:00
aa8908c52f
Multiplication all the way to simulation.
2000-01-13 03:35:35 +00:00
fac3bde2c8
Elaborate parameters afer binding of overrides.
2000-01-10 01:35:23 +00:00
65ae92859c
NetConst can now hold wide constants.
1999-12-17 03:38:46 +00:00
76655ce2bb
Allow memories without indices in expressions.
1999-12-12 06:03:14 +00:00
3e2bb85f58
Synthesize LPM_RAM_DQ for writes into memories.
1999-12-05 02:24:08 +00:00
e96e8c62be
NetESignal object no longer need to be NetNode
...
objects. Let them keep a pointer to NetNet objects.
1999-11-28 23:42:02 +00:00
4cfa3e4047
Support the creation of scopes.
1999-11-27 19:07:57 +00:00
26288eeeb4
Detect and list scope names.
1999-11-24 04:01:58 +00:00
a81dcd7955
Support memories in continuous assignments.
1999-11-21 00:13:08 +00:00
513ade9b95
Support combinatorial comparators.
1999-11-14 23:43:45 +00:00
1624afe1ba
Add support for the LPM_CLSHIFT device.
1999-11-14 20:24:28 +00:00
cb5fc54b5e
Patch to synthesize unary ~ and the ternary operator.
...
Thanks to Larry Doolittle <LRDoolittle@lbl.gov>.
Add the LPM_MUX device, and integrate it with the
ternary synthesis from Larry. Replace the lpm_mux
generator in t-xnf.cc to use XNF EQU devices to
put muxs into function units.
Rewrite elaborate_net for the PETernary class to
also use the LPM_MUX device.
1999-11-04 03:53:26 +00:00
50e47c4173
Elaborate combinational UDP devices.
1999-11-04 01:12:41 +00:00
89881adece
Add the synth functor to do generic synthesis
...
and add the LPM_FF device to handle rows of
flip-flops.
1999-11-01 02:07:40 +00:00
e1bbbe5614
Include subtraction in LPM_ADD_SUB device.
1999-10-31 20:08:24 +00:00
71ecf8c143
Add to netlist links pin name and instance number,
...
and arrange in vvm for pin connections by name
and instance number.
1999-10-31 04:11:27 +00:00
70a1236626
Structural case equals device.
1999-10-10 01:59:54 +00:00
11eccfc033
Fix dump of sase statements.
1999-10-08 02:00:35 +00:00
f949f96df1
Add non-const bit select in l-value of assignment.
1999-10-07 05:25:33 +00:00
1d215998b2
Move the rvalue into NetAssign_ common code.
1999-10-06 05:06:16 +00:00
4d8c0c79d6
Add support for reduction NOR.
1999-10-05 06:19:46 +00:00
c63a3acf93
Elaborate ~^ and ~| operators.
1999-09-30 02:43:01 +00:00
a64a33e65a
Full case support
1999-09-29 18:36:02 +00:00
349f9ae302
Support parameters that reference other paramters.
1999-09-21 00:13:40 +00:00
3a5e55b229
Elaborate parameters in phases.
1999-09-20 02:21:10 +00:00
1f44822510
dump the repeat count, if applicable.
1999-09-19 01:06:36 +00:00
b04148b754
Elaborate non-blocking assignment to memories.
1999-09-15 01:55:06 +00:00
8f68a07476
Add support for delayed non-blocking assignments.
1999-09-04 19:11:45 +00:00
41a1c6bb02
elaborate the binary plus operator.
1999-09-03 04:28:38 +00:00
9f7eb4a935
Handle recursive functions and arbitrary function
...
references to other functions, properly pass
function parameters and save function results.
1999-09-01 20:46:19 +00:00
e69345b9fe
Elaborate and emit to vvm procedural functions.
1999-08-31 22:38:29 +00:00
23acca48ff
elaborate some aspects of functions.
1999-08-25 22:22:41 +00:00
71d35f32b2
Parse and elaborate rise/fall/decay times
...
for gates, and handle the rules for partial
lists of times.
1999-08-01 16:34:50 +00:00
93a77a2efd
Elaborate task input ports.
1999-07-24 02:11:19 +00:00
a5921ceae8
netlist support for ternary operator.
1999-07-17 19:50:59 +00:00
3ff6912bdd
Elaborate user defined tasks.
1999-07-03 02:12:51 +00:00
853ad247a1
Elaborate and supprort to vvm the forever
...
and repeat statements.
1999-06-19 21:06:16 +00:00
e699787de9
Handle total lack of signals or nodes.
1999-06-15 05:38:15 +00:00
1464851e0e
Add support for procedural concatenation expression.
1999-06-09 03:00:05 +00:00
7605a7b1f0
Add parse and elaboration of non-blocking assignments,
...
Replace list<PCase::Item*> with an svector version,
Add integer support.
1999-06-06 20:45:38 +00:00
ac6e15aeae
Compilation warning.
1999-05-31 15:46:20 +00:00
982cce6086
Exressions are trees that can duplicate, and not DAGS.
1999-05-30 01:11:46 +00:00
fe8ca1f72f
translate the letter synonyms for operators.
1999-05-17 04:53:47 +00:00
5de9b7c9f1
Parse and elaborate the concatenate operator
...
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
df0c894cb0
Excesss endl.
1999-05-06 02:29:32 +00:00
b44ef063a8
Fix handling of null delay statements.
1999-05-05 03:04:46 +00:00
5d00f17448
Handle wide events, such as @(a) where a has
...
many bits in it.
Add to vvm the binary ^ and unary & operators.
Dump events a bit more completely.
1999-05-01 20:43:55 +00:00
41f9a84a4b
Handle much more complex event expressions.
1999-05-01 02:57:52 +00:00
09cfbc6240
Core handles subsignal expressions.
1999-04-25 00:44:10 +00:00
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
b7f833dd71
Support more operators, especially logical.
1999-03-15 02:43:32 +00:00
13a6f05463
Prevent the duplicate allocation of ESignal objects.
1999-03-01 03:27:53 +00:00
e2a37a8ccd
Add support for module parameters.
1999-02-21 17:01:57 +00:00
e5f5f41515
Elaborate gate ranges.
1999-02-15 02:06:15 +00:00
30a3953c85
Turn the NetESignal into a NetNode so
...
that it can connect to the netlist.
Implement the case statement.
Convince t-vvm to output code for
the case statement.
1999-02-08 02:49:56 +00:00
8bdd381cdf
Parse and elaborate the Verilog CASE statement.
1999-02-03 04:20:11 +00:00
a7ad8985ac
Carry some line info to the netlist,
...
Dump line numbers for processes.
Elaborate prints errors about port vector
width mismatch
Emit better handles null statements.
1999-02-01 00:26:48 +00:00
63a8b4abe2
Function to calculate wire initial value.
1998-12-20 02:05:41 +00:00
10b345bd16
Fully elaborate Sequential UDP behavior.
1998-12-14 02:01:34 +00:00
9a73433759
Generate OBUF or IBUF attributes (and the gates
...
to garry them) where a wire is a pad. This involved
figuring out enough of the netlist to know when such
was needed, and to generate new gates and signales
to handle what's missing.
1998-12-07 04:53:16 +00:00
ada45acb0c
Add the nobufz function to eliminate bufz objects,
...
Object links are marked with direction,
constant propagation is more careful will wide links,
Signal folding is aware of attributes, and
the XNF target can dump UDP objects based on LCA
attributes.
1998-12-02 04:37:13 +00:00
e097c999d5
Elaborate UDP devices,
...
Support UDP type attributes, and
pass those attributes to nodes that
are instantiated by elaboration,
Put modules into a map instead of
a simple list.
1998-12-01 00:42:13 +00:00
af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve