4068c172f4
Fix overzealous detection of duplicate net/variable declarations.
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As reported by Larry Doolittle on iverilog-devel.
2015-06-07 08:48:33 +01:00
578a2543f7
Fix for br975 - assertion failure due to duplicate declaration of struct var.
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Added proper error handling for duplicate declarations of all variable
types.
2015-05-17 20:54:53 +01:00
c6e618350d
Fix for GitHub issue #60 (part 1) - reject numeric constant with zero size.
2015-04-26 11:04:02 +01:00
46c41f9be2
ivl: Enum type can be used in port declarations.
2015-02-05 17:17:33 +01:00
bcca3cf395
ivl: Unpacked array typedefs are correctly recognized when used in function parameters.
2015-02-04 15:58:12 +01:00
b6e16aea6b
ivl: Typedefs may use unpacked arrays.
2015-01-12 11:08:31 +01:00
bca84d9dbb
Added parser support for SV modport declarations.
2015-01-10 11:10:41 +00:00
b400532169
Added support for interface declaration and instantiation.
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modport and extern tf declarations are not yet supported.
2014-12-19 23:10:14 +00:00
8fd1ead082
Revert "ivl: Allow to initialize variables with other variables (since Verilog-2001)."
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This reverts commit 610ca95cbe
2014-12-03 08:27:01 -08:00
610ca95cbe
ivl: Allow to initialize variables with other variables (since Verilog-2001).
2014-11-27 17:36:23 +01:00
632e15a55c
Catch enumerations with the same name.
2014-10-31 20:06:28 -07:00
c25538d750
Pass the integer type for enumerations to the IVL target stage
2014-10-31 18:09:19 -07:00
23238aa7ac
Handle functions in $root scope.
2014-10-02 15:04:14 -07:00
c5fee8bdb9
Elaborate root tasks/functions.
2014-09-30 16:06:32 -07:00
fa21527e9f
Classes in $root scope up to elaboration.
2014-09-15 17:37:30 -07:00
853512868b
Merge branch 'x-mil15'
2014-09-08 21:10:14 -07:00
ec2793c9b0
Warn that classes defined in the compilation unit scope are not supported
2014-09-08 16:59:18 -07:00
9fa764285a
foreach multiple indices through the pform.
2014-08-30 10:18:57 -07:00
a67f18f8ef
ivl: Do not delete range objects right after setting range for a net.
2014-08-28 10:02:56 +02:00
5de83906f7
Sorry message for multi-dimension foreach loop indices.
2014-08-21 20:34:55 -07:00
f602ae84ab
Elaborate foreach loops as synthetic for loops.
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Create an implicit scope to hold the index variable, and
generate a for loop to perform the functionality of the
foreach.
2014-08-21 16:44:46 -07:00
588409389e
SV: Add support for var decls in unnamed begin/end blocks.
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SystemVerilog allows variables to be declared in unnamed begin/end
blocks. This patch adds support for this functionality.
2014-07-22 18:58:23 -07:00
14f597acdd
Add support for synthesis translate meta-comments.
2014-07-15 18:03:40 -07:00
0611135758
Some more cppcheck cleanup/updates
2014-06-29 20:39:40 -07:00
d96e8872c1
Fix for GitHub issue 25 - compiler crash when function declared outside module.
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This is an error in traditional Verilog and a unsupported feature in
SystemVerilog. Fail gracefully with a suitable error/sorry message.
Do the same for task declarations.
2014-05-23 21:55:46 +01:00
6caa41cc93
First pass at support for continuous assign of unpacked net arrays.
2014-04-06 08:40:09 -07:00
f8e33b12cd
Clean up pform_module_define_port in preparation for new tricks.
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Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
2014-04-06 08:40:09 -07:00
a849249a86
Allow typedefs to override inherited type names.
2014-04-06 08:40:08 -07:00
3e95966d70
More spelling fixes
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Mostly comments
Changs "initilzers" in a string visible with debug_elaborate.
Includes a few British->American changes in the root directory only.
2014-01-30 16:43:17 -08:00
be17bfc0e9
Spelling fixes
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Mostly comments.
One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-30 15:34:20 -08:00
a3b29dd70b
Handle enumeration literals that are in $root.
2014-01-11 19:19:14 -08:00
b0491b9c54
Handle typedefs in $root scope.
2014-01-11 19:19:14 -08:00
819770a6c4
Handle enumerations as packed struct/union members.
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There were also some subtleties related to using enumerations
from typedefs and using them in multiple places. Fix various
bugs related to those issues.
2013-12-07 12:20:28 -08:00
9a116498a2
Handle task/function default expressions in parsing/pform.
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This gets it to (but not through) the elaborator.
2013-09-20 20:44:56 -07:00
07cc18284c
Fix print token/argument mismatches and other cppcheck fixes
2013-09-09 13:34:38 -07:00
503487e9ea
Fix for br932 - support string types in task input ports.
2013-06-13 23:18:23 +01:00
6364aba975
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 09:16:24 +01:00
71c6193ff1
Finish adding support for end labels in SystemVerilog
2013-05-14 15:01:54 -07:00
51d3c03922
A time variable is always unsigned and pass the integer property
2013-04-30 14:05:19 -07:00
de6c57d661
Elaborate classes in lexical order so that mutual references work.
2013-04-28 16:28:24 -07:00
20ee350601
Generalize user defined function return type handling.
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I'm gonna need functions to return class objects, so generalize
the output types of user defined functions.
2013-04-20 16:38:35 -07:00
4ad556d464
Update some copyright notices.
2013-04-08 18:35:37 -07:00
4dffd97d28
Handle tasks in packages.
2013-04-08 18:20:39 -07:00
b1d853bf9b
Fix handling of struct members for variables imported from packages.
2013-04-08 18:20:39 -07:00
eba3d407ca
packages can contain variables.
2013-04-08 18:20:39 -07:00
bae0f1d3a7
Parse more package items
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Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
2013-04-08 18:20:39 -07:00
bdfd5b9b55
Add -g2012 flag and keywords for IEEE 1800-2012.
2013-04-02 14:41:44 -07:00
17330a3073
Elaborate class task and function methods.
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The parse of class methods already works, this patch forms
the methods into their own scopes, and elaborates those scopes.
The "this"
2013-03-24 15:12:35 -07:00
25b48fa790
Remove svector template from port handling.
2013-03-24 15:03:52 -07:00
e437321ea7
Fix implicit casts in assignments (part 6).
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IVL_VT_NO_TYPE is now used to signal an untyped LHS in a parameter
declaration. The parser function that handles specparam declarations
needs to do this too. Also, although it should never happen, make
sure we don't set the expression width in a NetECast object to a
negative number. Make constant evaluation of NetECast objects
observe the expression width.
2013-03-24 13:51:10 -07:00
Martin Whitaker
Maciej Suminski
Martin Whitaker
Stephen Williams
Cary R
Larry Doolittle