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8247 Commits

Author SHA1 Message Date
Martin Whitaker 3de7c234f7 Implement vpi_put_value() for named events (GitHub issue #158). 2017-06-15 08:47:29 +01:00
Martin Whitaker 8a5cbd4415 Fix for GitHub issue #152 - segfault on gate connection syntax error. 
If there is a syntax error in the source code, pform_makegate may be
passed a null list of port connections. The error is already reported,
so we just need to ignore it.
 2017-04-21 21:37:17 +01:00
Stephen Williams 0f57cceecc Merge pull request #154 from 8tab/depfile 
Return if unable to open dependencies file
 2017-04-10 09:43:05 -07:00
8tab cac5388451 Return if unable to open dependencies file 
Return and print an error if iverilog is unable to open dependencies
file. User can pass e.g path to existing directory in '-M' option,
which makes fopen to return NULL followed by crash in fclose.
 2017-04-09 23:18:49 +02:00
Stephen Williams 02ed16a50e Merge pull request #151 from tumik/master 
Added an option for ignoring errors about missing modules
 2017-03-22 15:33:58 -07:00
Mikael Tuomisalo c967ed238c Added option for ignoring errors about missing modules 2017-03-21 17:34:44 +02:00
Stephen Williams 135b7fba7e Merge pull request #149 from jersey99/master 
Add support to handle attributes at module instantiation sites.
 2017-03-16 09:38:04 -07:00
Vamsi Vytla cfd3b893be Add support to handle attributes at module instantiation sites. 
(* my_fancy_attribute *)
foobar1 foobar (clk(clk), rst(rst) ...);

  - Modifies PGModule to hold the attribute map (can be verified with pform_dump)
  - pform_make_modgate(s) bind the attributes from the parser to the above map
  - The attributes from PGModule are inserted into the NetScope of that module
    PGModule::elaborate_scope_mod_instances_
  - Currently these attributes automatically make it into netlist
  - These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val
    from ivl_target.h
 2017-03-16 07:41:10 -07:00
Stephen Williams fbd69e1774 Merge pull request #148 from Jesus89/mingw-fix 
Fix x86_64-w64-mingw32 build: undefined ___strtod
 2017-02-27 15:12:12 -08:00
Jesús Arroyo Torrens bef04508f2 Fix x86_64-w64-mingw32 build: undefined ___strtod 2017-02-24 10:43:30 +01:00
Stephen Williams a427440054 Merge branch 'master' of github.com:steveicarus/iverilog 2017-02-17 10:40:14 -08:00
Johann Klammer 8bccbe7cb5 fix for const eval 2017-02-17 09:55:39 -08:00
Martin Whitaker 3c91630b53 Improved error checking for defparam values supplied on the command line. 
Fixes GitHub issue #139 plus various assertion failures when invalid
values are specified.
 2017-01-29 20:13:01 +00:00
Martin Whitaker 8f6f999ea7 Fix for GitHub issue #142 - assertion failure when parameter expression 
contains undefined variable.
 2017-01-29 10:47:54 +00:00
Martin Whitaker 4e2ba29dc6 Add library search path option to iverilog-vpi (GitHub issue #145). 2017-01-29 09:32:14 +00:00
Stephen Williams 221084d838 Sorry message for procedural assertion statements. 2017-01-10 11:38:38 -08:00
Cary R 3d9e777ae5 Allocate the correct amount of memory when escaping a string 2017-01-08 20:46:20 -08:00
Johann Klammer c79df7c44b fix failing VPI callbacks the vpip_cur_task was left dangling 2017-01-01 17:44:54 -08:00
Stephen Williams 6e5558e67d Trivial fixes to pform dumps. 2016-12-29 09:39:45 -08:00
Stephen Williams 063ae77568 Merge pull request #132 from Fatsie/master 
[vhdlpp]Added to_bit and to_bitvector standard functions
 2016-11-29 08:59:51 -08:00
Staf Verhaegen 447f941f35 [vhdlpp]Added to_bit and to_bitvector standard functions 2016-11-27 01:28:39 +01:00
Martin Whitaker b4e8a12309 Fix for GitHub issue #128 - disable CONCATZ generation for vhdl target. 2016-11-25 22:23:58 +00:00
Martin Whitaker 7cac4677bf Fix for GitHub issue #130 part 2 : assertion failure on unsupported cast. 2016-11-25 22:11:13 +00:00
Martin Whitaker 002f118bb5 Fix for GitHub issue #130 part 1 - null dereference when assigning int to enum. 2016-11-25 21:53:35 +00:00
Henry Wong 182c08b528 Fix segfault when error in multi-dimensional part select. 2016-10-27 10:59:31 -07:00
Henry Wong 69a96112e8 Fix null-pointer when trying to dump null statements. 2016-10-27 10:55:50 -07:00
Henry Wong f827e4f748 Pop current_block_stack after for_variable_declaration and foreach. 2016-10-27 10:29:18 -07:00
Martin Whitaker 991d7d7582 Fix indentation in previous patch. 2016-10-20 16:25:34 +01:00
Henry Wong 1f9bf656ed Adding implementation of NetEvWait::nex_input to handle event controls inside always@(*) blocks 2016-10-20 16:19:55 +01:00
Martin Whitaker a9f1f306f1 Replace strndup with strdup and fix a few potential buffer overrun bugs. 
strndup is not available in Windows.
 2016-10-14 22:19:33 +01:00
Martin Whitaker edb922f613 Use correct format strings for PLI_UINT64 in printf/scanf functions. 2016-10-14 20:35:36 +01:00
Martin Whitaker 7ddc514518 Allow library files to be specified on the iverilog command line. 
This was already supported in command files, using the '-v' flag.
'-v' is already in use on the command line, so use '-l' instead,
and make that an alias for '-v' in command files.
 2016-10-02 18:57:32 +01:00
Martin Whitaker 0fdf29e099 Fix for GitHub issue #117 - delays in VPI simulation time callbacks. 
Change cbReadWriteSynch and cbReadOnlySynch to interpret the passed
time value as a relative delay, not an absolute time. This matches
the behaviour of other simulators.
 2016-09-25 20:43:58 +01:00
Stephen Williams e56e52bc42 Merge branch 'master' of github.com:steveicarus/iverilog 2016-09-19 12:59:41 -07:00
Maciej Suminski f32b64f497 Fixed warnings about shifting a negative value 2016-09-19 12:54:15 -07:00
Maciej Suminski 151f061298 vhdlpp: Removed unused parameters to mute warnings 2016-09-19 12:53:41 -07:00
Maciej Suminski 3710d35dd1 Added missing brackets 2016-09-19 12:53:06 -07:00
Maciej Suminski aaf0a9e623 vhdlpp: Accept uppercase letters in based literals 2016-09-19 12:46:24 -07:00
Martin Whitaker 080dd0323d Fix for GitHub issue #127 - coerce output ports to inout when necessary. 2016-09-17 19:20:48 +01:00
Cary R 5853e32f82 Fix some cppcheck warning issues 2016-09-13 23:45:25 -07:00
Cary R c706c5dd90 The array properties can be available in a constant context 
For most arrays the various properties are available as constant
values and can be evaluated in the compiler.
 2016-09-11 14:25:00 -07:00
Martin Whitaker 3c9b39846c Use gn_system_verilog() where appropriate. 
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
 2016-09-08 23:00:48 +01:00
Stephen Williams 301e85a8ca Merge pull request #122 from orsonmmz/resize_fix 
vhdlpp update
 2016-09-02 10:01:02 -07:00
Maciej Suminski 5dd2e6a7c8 vhdlpp: Corrected standard library function headers 2016-09-01 12:08:44 +02:00
Maciej Suminski 8ba3d62071 vhdlpp: Better resize() implementation. 
Previous version did not work well with signed expressions or expressions that
were temporarily resized (e.g. a + 32'd42, where a is a[7:0]).
 2016-09-01 12:08:44 +02:00
Maciej Suminski bab39dae19 vhdlpp: Some of the standard library functions are imported only on request 
Previously they have been always enabled, now it is required to put a
'use' directive.
 2016-09-01 12:08:44 +02:00
Maciej Suminski 089dd037d6 vhdlpp: Use the wider variable size for arith operations on (un)signed 2016-09-01 12:08:44 +02:00
Maciej Suminski 25f4a54852 vhdlpp: Subprograms are matched once. ExpFunc::probe_type() return exact type 2016-09-01 12:08:44 +02:00
Maciej Suminski 8f86004100 vhdlpp: Clearer error messages 2016-09-01 12:08:44 +02:00
Maciej Suminski 07543315cf vhdlpp: Stricter array type matching 
Arrays type match if they have a common parent, instead of the
element type. Now (un)signed & std_logic_vector types do not match,
as it should be in VHDL.
 2016-09-01 12:08:43 +02:00