iverilog

Commit Graph

Author	SHA1	Message	Date
steve	248baa26e1	Move all file manipulation out of target class.	2000-08-09 03:43:45 +00:00
steve	d58533fd7b	target methods need not take a file stream.	2000-08-08 01:50:42 +00:00
steve	3aa250b16b	Report code generation errors through proc_delay.	2000-07-29 16:21:08 +00:00
steve	b1fd927acb	Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.	2000-04-12 04:23:57 +00:00
steve	b734ecf02f	Macintosh compilers do not support ident.	2000-02-23 02:56:53 +00:00
steve	0955058fbe	Catch parallel blocks in vvm emit.	1999-09-22 16:57:23 +00:00
steve	71d35f32b2	Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.	1999-08-01 16:34:50 +00:00
steve	3ff6912bdd	Elaborate user defined tasks.	1999-07-03 02:12:51 +00:00
steve	6a823cde59	Unify the NetAssign constructors a bit.	1999-06-13 16:30:06 +00:00
steve	41f9a84a4b	Handle much more complex event expressions.	1999-05-01 02:57:52 +00:00
steve	e097c999d5	Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.	1998-12-01 00:42:13 +00:00
steve	af8d6fbf01	NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.	1998-11-23 00:20:22 +00:00
steve	3fb7a053be	Introduce verilog to CVS.	1998-11-03 23:28:49 +00:00

13 Commits