Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Infrastructure for debug and emit of sequential statements in processes.
This does not properly handle the actual semantics of the behavioral
code, but it provides an infrastructure where we can handle all the
tricky elaboration to come.
Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.
Also add a few missing expression types.
Significant rework of scope management to unify the handling of
types in the ieee library and types/constants/components in packages.
This involved adjusting the parser rules to manage a stack of scopes
and rewriting the IEEE library support to not use global maps for
the loaded types.
There has been added additional default attribute to
all 'dump' function calls which is in all cases equal
to 0. Now one can specify how much this debug dumping should
be intended. This should allow people to dump smoothly whole
designs (as it was now) as far as separate units.
This is now the parent who specifies the base indentation
for all components (children). For example, architecture
"decides" how much their signals should be indented.
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.
Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
There are internal types that are unbounded arrays. Allow subtype
syntax that creates bounded versions of these arrays, and elaborate
them as vectors at port boundaries. This makes some interesting types
work out.
Also start replacing vhdlint and vhdlreal with int64_t and double,
which are reasonable values for universal_integer and universal_real
from the VHDL standard. I need these cleaned up because the ints in
particular are used for the literal expressions in array index constraints.
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
Stephen Williams
Pawel Szostek
Pawel Szostek
Larry Doolittle