3ff6912bdd
Elaborate user defined tasks.
1999-07-03 02:12:51 +00:00
33d4133217
Add the === and !== binary operators.
1999-06-24 04:21:45 +00:00
853ad247a1
Elaborate and supprort to vvm the forever
...
and repeat statements.
1999-06-19 21:06:16 +00:00
f69becd5e0
Do not bother trying to print lvalue name in comment.
1999-06-10 04:03:43 +00:00
1464851e0e
Add support for procedural concatenation expression.
1999-06-09 03:00:05 +00:00
4932dc7c5e
Support non-blocking assignment down to vvm.
1999-06-07 02:23:31 +00:00
295306aad5
emit NetAssignMem objects in vvm target.
1999-05-12 04:03:19 +00:00
9e82ed240c
Restore support for wait event control.
1999-05-03 01:51:29 +00:00
5d00f17448
Handle wide events, such as @(a) where a has
...
many bits in it.
Add to vvm the binary ^ and unary & operators.
Dump events a bit more completely.
1999-05-01 20:43:55 +00:00
41f9a84a4b
Handle much more complex event expressions.
1999-05-01 02:57:52 +00:00
4b73655537
Generate SubSignal refrences in vvm.
1999-04-25 22:52:32 +00:00
d3350c9b27
Add to vvm proceedural memory references.
1999-04-22 04:56:58 +00:00
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
b7f833dd71
Support more operators, especially logical.
1999-03-15 02:43:32 +00:00
a2bc27318f
Handle default case.
1999-02-22 03:01:12 +00:00
e5f5f41515
Elaborate gate ranges.
1999-02-15 02:06:15 +00:00
fef81958bc
Do not generate code for signals,
...
instead use the NetESignal node to
generate gate-like signal devices.
1999-02-08 03:55:55 +00:00
30a3953c85
Turn the NetESignal into a NetNode so
...
that it can connect to the netlist.
Implement the case statement.
Convince t-vvm to output code for
the case statement.
1999-02-08 02:49:56 +00:00
d1e2b036fc
Add startup after initialization.
1999-01-01 01:46:01 +00:00
63a8b4abe2
Function to calculate wire initial value.
1998-12-20 02:05:41 +00:00
4e2c0036aa
VVM support for small sequential UDP objects.
1998-12-17 23:54:58 +00:00
af8d6fbf01
NetAssign handles lvalues as pin links
...
instead of a signal pointer,
Wire attributes added,
Ability to parse UDP descriptions added,
XNF generates EXT records for signals with
the PAD attribute.
1998-11-23 00:20:22 +00:00
7859de1e4e
Add support it vvm target for level-sensitive
...
triggers (i.e. the Verilog wait).
Fix display of $time is format strings.
1998-11-10 00:48:31 +00:00
ebad845fc3
Add procedural while loops,
...
Parse procedural for loops,
Add procedural wait statements,
Add constant nodes,
Add XNOR logic gate,
Make vvm output look a bit prettier.
1998-11-09 18:55:33 +00:00
47a444fb92
Calculate expression widths at elaboration time.
1998-11-07 19:17:10 +00:00
b118634189
Handle procedural conditional, and some
...
of the conditional expressions.
Elaborate signals and identifiers differently,
allowing the netlist to hold signal information.
1998-11-07 17:05:05 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve