Static properties are like variables in a named scope.
Detect these variables during elaboration so that the
code generator just sees them as variables.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
For constant word indices, issue a warning if the index is out of
range or an undefined value. In any case, the RHS value should be
discarded, and the actual assignment should be skipped.
If a logical pull device is converted into a CA then it is an assignment
with strength, so just emit the appropriate constant to get the correct
functionality (e.g. 1'b1 for a pull up and 1'b0 for a pull down).
Also add missing file/line information.
Add support for case, forever, and repeat statements in constant
functions. Also fix a bug in the constant function implementation
of NetESelect when used for zero/sign extension.
The compiler was treating case and case item expressions as
self-determined. They should be context-sensitive, just like
the operands of a comparison operation.
This patch implements the evaluate_function method for the NetDisable
and NetSTask classes. It also makes the checks for a function being
constant work when the function contains nested scopes (named blocks).
SystemVerilog allows a function to be called without an assignment for
the return value. This patch adds a warning that Icarus does not currently
support this and provides a place to add this functionality later.
This involves working out the code to get the base type of a select
expression of a darray. Also added the runtime support for darrays
with real value elements.
These two typedefs exactly matched earlier ones in the same scope and
gcc was complaining that they were shadowing the previous definitions.
Since the definitions matched exactly just deleting the second
typedef was acceptable.
Added: basic vpiPort VPI Objects for vpiModulkes
vpiDirection, vpiPortIndex, vpiName, vpiSize attributes
Since ports do not exist as net-like entities (nets either side
module instance boundaries are in effect connect directly in
the language front-ends internal representation) the port information
is effectively just meta-data passed through t-dll interface and
output as a additional annotation of module scopes in vvp.
Added: vpiLocalParam attribute for vpiParameter VPI objects
Added: support build for 32-bit target on 64-bit host (--with-m32
option to configure.in and minor tweaks to Makefiles and systemc-vpi).
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
When a conditional statement is unnamed, it doesn't create a scope
and we get into "direct" generate scheme elaboration. This direct
elaboration needs to handle case generate schemes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Cary R
Stephen Williams
Martin Whitaker
Arun Persaud
Andrew Stevens
Martin Whitaker