Nick Gasson
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38de6ebf3a
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Compress support function definitions a bit
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2008-07-19 21:04:52 +01:00 |
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Nick Gasson
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ef89a760d6
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Add vhdl_element::print method for debugging
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2008-07-01 10:44:20 +01:00 |
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Nick Gasson
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050aa277ae
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Make vhdl_element::emit a little more generic
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2008-07-01 10:37:22 +01:00 |
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Nick Gasson
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1d28b935e8
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Split vhdl_element.cc into multiple files
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2008-06-08 13:27:48 +01:00 |
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Nick Gasson
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4b4a1c6cac
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Tidy up type casting
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2008-06-08 12:55:18 +01:00 |
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Nick Gasson
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110a1b2ac7
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Replace type classes with enumeration
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2008-06-08 12:48:56 +01:00 |
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Nick Gasson
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fbf85398da
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Support converting bit strings to std_logic
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2008-06-07 16:19:10 +01:00 |
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Nick Gasson
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c064ae6bc3
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Generate VHDL for non-blocking assignments
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2008-06-07 14:54:00 +01:00 |
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Nick Gasson
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39228f3495
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VHDL AST element for non-blocking assignment
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2008-06-07 14:31:33 +01:00 |
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Nick Gasson
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066a9b7a61
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Add AST element for function call expressions
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2008-06-07 13:29:27 +01:00 |
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Nick Gasson
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cdb180e1d4
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Associate a type with each VHDL expression node
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2008-06-07 13:23:21 +01:00 |
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Nick Gasson
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a8ecce7421
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Make sure all declarations have a type
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2008-06-07 12:15:46 +01:00 |
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Nick Gasson
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96cf190720
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Generate signals and sensitivity list for @(..) statement
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2008-06-06 17:56:52 +01:00 |
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Nick Gasson
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373832ba22
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Specify correct sensitivity list
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2008-06-06 17:36:15 +01:00 |
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Nick Gasson
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d36bbec5b5
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Generate VHDL for no-op statements
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2008-06-05 13:16:35 +01:00 |
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Nick Gasson
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7bd1565cfb
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$display now (mostly) working
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2008-06-04 20:42:44 +01:00 |
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Nick Gasson
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6e448da90d
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Emit Write() calls for parameters of $display
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2008-06-04 15:19:44 +01:00 |
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Nick Gasson
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4bf2e1669d
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Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
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2008-06-04 13:52:56 +01:00 |
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Nick Gasson
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dd30c1b39d
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Support procedure call generation for $display
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2008-06-04 13:27:42 +01:00 |
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Nick Gasson
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94006cb44c
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Working on code generation for $display task
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2008-06-03 19:46:10 +01:00 |
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Nick Gasson
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2e6ec91ce0
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Scalar types
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2008-06-03 19:20:45 +01:00 |
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Nick Gasson
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f9e1289463
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Tidy up vhdl_element.cc
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2008-06-03 17:43:54 +01:00 |
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Nick Gasson
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a09b4e3b92
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Initial process have wait at the end
(do it properly this time rather than a hack :-)
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2008-06-03 17:39:24 +01:00 |
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Nick Gasson
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ab6ae621cb
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Remove useless comments in output
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2008-06-02 20:24:25 +01:00 |
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Nick Gasson
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041925c123
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Component instantiation to replicate Verilog hierarchy
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2008-06-02 17:45:58 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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5cbd587833
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Clean up generated objects
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2008-05-31 16:08:57 +01:00 |
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Nick Gasson
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8189c4ee43
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Generate VHDL entities and architectures for all module scopes
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2008-05-31 15:28:25 +01:00 |
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Nick Gasson
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e38494a10c
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Pretty-print VHDL output
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2008-05-29 16:24:16 +01:00 |
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Nick Gasson
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bfa2bfc8ae
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Makefile and autoconf changes to build VHDL code generator
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2008-05-28 17:17:39 +01:00 |